ics9db102 Integrated Device Technology, ics9db102 Datasheet
ics9db102
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ics9db102 Summary of contents
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... Description 1-to-2 Zero-delay or fanout buffer for PCI Express.The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking ...
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... POWER Ground pin for the PLL core. POWER 3.3V power for the PLL core. 2 Pin Number Description GND 6,15 PCI Express Outputs Analog VDD & GND for PLL core DESCRIPTION ICS9DB102 SMBUS IREF REV G 12/14/07 ...
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... V MIN TYP MAX 0 0.3 0 -200 75 100 100 101 7 5 4.5 1 2.7 5.5 0.4 4 1000 300 ICS9DB102 UNITS NOTES MHz kHz 1 KHz ...
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... =50Ω. REF OH O ICS9DB102 UNITS NOTES Ω 1 1,3 mV 1,3 1,3 mV 1,3 mV 1,3 mV 1,3 ppm 1 1 ...
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... PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz 5 Min Typ Max Units Notes 0 1 2 1,4 2 2.5 3 MHz 1,5 0.4 0.5 1 MHz 1,5 40 108 ps 1,2,3 2.7 3.1 ps rms 1,2,3 2.2 3.1 ps rms 1,2,3 1 rms 1,2,3 ICS9DB102 REV G 12/14/07 ...
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... Dimension or Value Unit Figure 2 min to 16 max inch 1 1.8 min to 14.4 max inch 1 Dimension or Value Unit Figure 0. max inch 2 0.225 min to 12.6 max inch 2 L4 L4’ PCI Ex Board Down Device REF_CLK Input L4 L4’ PCI Ex Add In Board REF_CLK Input ICS9DB102 REV G 12/14/07 ...
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... L2 R3 R1a L2’ R1b R2a R2b L3’ L3 Note 3.3 Volts R5a R5b Cc Cc R6a R6b 7 Figure 3. Note ICS874003i-02 input compatible Standard LVDS R4 L4 L4’ Down Device REF_CLK Input PCIe Device REF_CLK Input ICS9DB102 REV G 12/14/07 ...
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... ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function General SMBus serial interface information for the ICS9DB102 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... RESERVED RW RESERVED RW RESERVED RW RESERVED RW RESERVED RW RESERVED RW RESERVED Functions controlled SMBus registers by device pins - - - - - Low BW High BW PLL enabled (ZDB mode) mode ICS9DB102 PWD PWD PWD REV G 12/14/07 ...
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... Control Type Function RW RW Writing to this register RW will configure how RW many bytes will be RW read back, default bytes PWD - - PWD - PWD - - ICS9DB102 REV G 12/14/07 ...
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... D SEE VARIATIONS E 5.80 6.20 3.80 4.00 e 0.635 BASIC L 0.40 1.27 N SEE VARIATIONS a 0° 8° SEE VARIATIONS ICS9DB102 In Inches MIN MAX .053 .069 .004 .010 -- .059 .008 .012 .007 .010 SEE VARIATIONS .228 .244 .150 .157 0.025 BASIC .016 .050 SEE VARIATIONS 0° 8° ...
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... E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS a 0° 8° aaa -- 0.10 D mm. N MIN MAX 20 6.40 6.60 ICS9DB102 In Inches MIN MAX -- .047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -- .004 ...
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... ICS9DB102 2 Output PCI Express* Buffer with CLKREQ# Function Revision History Rev. Issue Date Description 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. F 08/06/07 3. Added terminations tables. H 12/14/07 Updated General SMBus Interface Information. TM Innovate with IDT and accelerate your future networks. Contact: www ...