SCANSTA111SM National Semiconductor, SCANSTA111SM Datasheet - Page 22

• Manufacturer Part Number: SCANSTA111SM
• Manufacturer: National Semiconductor

Specifications of SCANSTA111SM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

www.national.com
during the UPDATE-DR state and the GPIO input values are
written to the corresponding GPIO register during the CAP-
TURE-DR state. Dedicated GPIO operation is not supported
in the silicon version of the 'STA111.
LSP SHARED: In the shared mode of operation, the dot1 LSP
pins TDI
and TDO
The sequence of operations to use shared GPIOs on an LSP
are as follows (example uses LSP
1.
2.
3.
4.
5.
6.
7.
ADDRESS INTERROGATION
The 'STA111 has four states that it can go to from the Wait-
For-Address state: Unselected, Singularly-selected, Multi/
Broadcast-selected, and Address-interrogation (see
13).
After a reset (or GOTOWAIT command) has been issued, the
'STA111 TAP is sequenced to the Capture-IR state where
XXXXXX01 is loaded into the shift register. Upon entering the
Shift-IR state, the instruction register is filled with the address
interrogation value (3A hex) which is loaded into the address
register as the TAP is sequenced into the Update-IR state.
On the next loop through Capture-IR the shift register is load-
ed with the ones-complement of the slot address. In the Shift-
IR state the address interrogation value is loaded into the
instruction register. The value presented on TDO
wired-and address of all of the 'STA111s on the bus. As this
value is being shifted out, each 'STA111 will monitor its
TDO
device shifts all bits of its ones-complement address and nev-
er gets a compare error it will tri-state TDO
Wait-For-Reset state. Alternately, if the device sees a com-
pare error while it is shifting its ones-complement address it
will stop shifting its address and tri-state TDO
shift operation; during the next Shift-IR operation it will again
try to present its address (if the previous instruction was 3A
hex) while monitoring TDO
IR-Scan the 'STA111 address into the instruction register
(address a 'STA111).
IR-Scan the MODESEL
register to select Mode Register
configuration register) as the data register.
DR-Scan 00000001 into Mode Register
GPIOs on LSP
TAP enters the RTI state at the end of this shift operation
(TDO
the default value in the Shared GPIO Register
IR-Scan the SGPIO
register to select the Shared GPIO Register
register.
DR-Scan 00000011 into the Shared GPIO Register
set TDO
Update-DR). During this operation, when the TAP enters
Capture-DR, the present value on the TDI
values of TDO
Register
register and will be scanned out 00000X00 (X = value
present on TDI
Step 5 can be repeated to generate waveforms on
TDO
as data, TDO
TAP state = Update-DR) and 00000X11 would be
scanned out (X = value present on TDI
Capture-DR).
IR-Scan the GOTOWAIT or SOFTRESET instruction, or
generate a TRST
B
to see if it is receiving the same value it is driving. If the
n
n
0
, TDO
0
are outputs, TDI
and TMS
and TMS
0
0
) will be captured into bits 2, 1 and 0 of the shift
and TMS
n
and TMS
0
0
and TMS
0
0
0
. The GPIOs will be enabled when the
and TMS
0
. If step 5 was repeated with 00000000
when TAP enters Capture-DR).
B
will be forced to logic 0 as defined by
0
reset to disable the GPIOs.
0
to a logic 1 (when TAP enters
instruction into the instruction
B
n
n
.
3
is an input in the GPIO mode.
0
pins become GPIO pins. TMS
instruction into the instruction
0
would be set to a logic 0 (when
(as set by Shared GPIO
0
):
3
(Shared GPIO
0
when TAP enters
3
B
to enable
B
0
and go to the
until the next
0
pin and the
as the data
B
0
).
will be a
Figure
0
to
n
22
Shifting 3A hex into the instruction registers of the 'STA111s
will continue until all 'STA111s have presented their address.
At this time all devices will be waiting to be reset, and if a 3A
is shifted into the 'STA111 instruction registers the address
read by the tester will be all weak 1s due to all TDO
tri-stated. Reading all ones will signal the tester that address
interrogation is complete. Since all ones signifies the end of
Address-Interrogation, no device can have an address of all
zeros (ones-complement).
If at any time, during the address interrogation mode, any
other instruction besides 3A hex is shifted into the instruction
register, then the 'STA111 will exit the interrogation mode.
Also, the 'STA111's state machine will go to the Wait-For-Ad-
dress state.
This address interrogation scheme presumes that TDO
capable of driving a weak 1 and that an 'STA111 driving a 0
will overdrive an 'STA111 driving a weak 1.
The following is an example of the Address-Interrogation
function. Assume there are three 'STA111s (U1, U2 and U3)
on a dot1 backplane with slot addresses 010100, 100000 and
000001 respectively (assuming 6 address pins).
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Again U1 and U2 drive weak 1 and the shift continues.
11. U2s weak 1 is overdriven by U1s 0 and U2 enters the
12. The shift operation continues and U1 finishes shifting its
13. The instruction shift operation is repeated and U2 shifts
14. The instruction shift operation is repeated, however, all
The 'STA111s are reset and the interrogation address/
op-code (3A hex) is shifted into the instruction registers.
At the end of the instruction shift (Update-IR) the 'STA111
address registers are loaded with 3A hex.
The TAPs are sequenced to Capture-IR and the shift
registers latch the ones-complement slot addresses
(U1=101011, U2=011111 and U3=111110).
The TAPs are sequenced to Shift-IR and the LSB of the
interrogation address is presented on the TDI
Concurrently, the LSBs of the ones-complement slot
addresses are presented on the respective TDO
The weak 1 being driven on U1 and U2 is overdriven by
the 0 from U3. U1 and U2 enter the Wait-For-Next-
Interrogation state.
The shift operation continues and U3 finishes shifting its
ones-complement address (111110) out on TDO
enters the Wait-For-Reset state when the TAP enters
Update-IR.
The TAPs are again sequenced to Capture-IR and U1
and U2 shift registers latch the ones-complement
addresses (U1=101011, U2=011111).
The TAPs are sequenced to Shift-IR and the LSB of the
interrogation address is presented on the TDI
Concurrently, the LSBs of the ones-complement
addresses are presented on the respective TDO
Since both U1 and U2 are driving a weak 1 the shift
continues.
Wait-For-Next-Interrogation state.
ones-complement address (101011) out on TDO
enters theWait-For-Reset state.
its ones-complement address (011111) out on TDO
enters the Wait-For-Reset state.
devices have been interrogated and are waiting for a
reset. The master device will receive all ones. This
implies that there can not be an STA111 with address 0!
B
B
's.
's.
B
's being
B
B
B
B
's.
's.
. U3
. U1
B
. U2
B
is