SCANSTA111SM National Semiconductor, SCANSTA111SM Datasheet - Page 15

• Manufacturer Part Number: SCANSTA111SM
• Manufacturer: National Semiconductor

Specifications of SCANSTA111SM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

GOTOWAIT: This instruction is used to return all 'STA111s
to the Wait-For-Address state. All unparked LSPs will be
parked in the Test-Logic-Reset TAP controller state (see
ure
MODESEL: The MODESEL instruction inserts Mode Regis-
ter
LSPN configuration for a device with up to five (5) LSPs (only
three in Silicon). Bit 7 of Mode Register
status flag.
MODESEL
ister
determines the LSPN configuration for LSP 5, 6 and 7 (if they
exist), and Mode Register
figuration.
MCGRSEL: This instruction inserts the multi-cast group reg-
ister (MCGR) into the active scan chain. The MCGR is used
to group 'STA111s into multi-cast groups for parallel TAP se-
quencing (i.e., to simultaneously perform identical scan op-
erations).
SOFTRESET: This instruction causes all 3 Port configuration
controllers (see
which forces TMS
Logic-Reset state within 5 TCK
LFSRSEL: This instruction inserts the linear feedback shift
register (LFSR) into the active scan chain, allowing a com-
pacted signature to be shifted out of the LFSR during the Shift-
DR state. (The signature is assumed to have been computed
during earlier LFSRON shift operations.) This instruction dis-
ables the LFSR register's feedback circuitry, turning the LFSR
into a standard 16-bit shift register. This allows a signature to
be shifted out of the register, or a seed value to be shifted into
it.
LFSRON: Once this instruction is executed, the linear feed-
back shift register samples data from the active scan path
(including all unparked TDI
0
5).
into the active scan chain. Mode Register
n
(n = 1 to 3) into the active scan chain. Mode Register
n
: The MODESEL
Figure
n
high; this parks each local port in the Test-
4) to enter the Parked-TLR state,
2
determines the Shared GPIO con-
n
) during the Shift-DR state. Data
FIGURE 9. Local Scan Port Synchronization from Parked-TLR State
n
instruction inserts Mode Reg-
B
cycles.
0
is a read-only counter
0
determines the
Fig-
1
15
from the scan path is shifted into the linear feedback shift
register and compacted. This allows a serial stream of data
to be compressed into a 16-bit signature that can subse-
quently be shifted out using the LFSRSEL instruction. The
linear feedback shift register is not placed in the scan chain
during this mode. Instead, the register samples the active
scan-chain data as it flows from the LSPN to TDO
LFSROFF: This instruction terminates linear feedback shift
register sampling. The LFSR retains its current state after re-
ceiving this instruction.
CNTRSEL: This instruction inserts the 32-bit TCK counter
shift register into the active scan chain. This allows the user
to program the number of n TCK cycles to send to the parked
local ports once the CNTRON instruction is issued (e.g., for
BIST operations). Note that to ensure completion of count-
down, the 'STA111 should receive at least n TCK
CNTRON: This instruction enables the TCK counter. The
counter begins counting down on the first rising edge of
TCK
decremented on each rising edge of TCK
the TCK counter reaches terminal count, 00000000 Hex,
TCK
Mode Register
If the CNTRON instruction is issued when the TCK counter is
00000000 (terminal count) the local TCKs of parked LSPs will
be gated. The counter will begin counting on the rising edge
of TCK
ue following a CNTRSEL instruction (see BIST Support in
Special Features section for an example).
CNTROFF: This instruction disables the TCK counter, and
TCK
DEFAULT_BYPASS: This instruction selects the Bypass
register to be the default for SCANSTA111 commands that
do not explicitly require a data register. The default after RE-
SET is the Device ID register.
B
n
n
control is returned to Mode Register
of all parked LSP's is held low. This function overrides
following the Update-IR TAP controller state and is
B
when the TCK counter is loaded with a non-zero val-
0
TCK control bit (bit-3).
B
0
thereafter. When
(bit 3).
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B
B
.
pulses.
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