SCANSTA111SM National Semiconductor, SCANSTA111SM Datasheet - Page 21

• Manufacturer Part Number: SCANSTA111SM
• Manufacturer: National Semiconductor

Specifications of SCANSTA111SM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

•
Throughout this datasheet, notations exist to clarify the dif-
ferences between features available on the Silicon version
and the HDL version.
KNOWN POWER-UP STATE
The 'STA111 has a known power-up condition. This is the
same state that the device is in after a TRST reset. This hap-
pens at power-up without the presence of a TCK
Reset can also occur via a 5 TMS high reset or a SOFTRE-
SET command.
POWER-OFF HIGH IMPEDANCE INPUTS AND OUTPUTS
The 'STA111 backplane test port features power-off high
impedance inputs and outputs.
The TDI
sistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
ing), these inputs appear to be a capacitive load to ground.
When V
appear to be capacitive with the pull-up to ground.
The TCK
diode (ESD is controlled with an alternate method). When the
device is power-off (V
capacitive load to ground. When V
but tied to V
ground.
When the device is power-off (V
TDO
Refer to the device IBIS model on our website for more details
about the I/O characteristics at http://www.national.com/ap-
pinfo/scan/ibis.html.
TRST
TRST
known power-up state.
TRST
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR state the TRST
states the TRST
PHYSICAL LAYER CHANGES
TRIST for TDO
nal buffer circuit between the 'STA111 and the backplane/
LSP. This would allow, for example, a CMOS-to-LVDS con-
verter to drive an LVDS JTAG backplane test bus. These
signals are always driving. A separate TRIST is provided for
each LSP to report a TRI-STATE on TDO when the LSP is
not in a shift state.
SVF DRIVEN, SELF-CHECKING TEST BENCH
The 'STA111 consists of 3 types of pins, dot1 backplane pins,
dot1 LSP pins and support pins. The command interpreter of
the test bench is able to translate a limited set of SVF com-
mands to the dot1 backplane pins. The SVF shift commands
Number/Type of GPIO bits: The 'STA111 has both
dedicated and shared GPIO (General Purpose I/O). Each
dedicated group of GPIO bits supports from 0 to 4
dedicated inputs and 0 to 4 dedicated outputs. There are
provisions for specifying the default (power-up) value.
TMS
functioning as LSP or GPIO. TMS
TDI
the 'STA111 is synthesized with shared GPIO on all three
available LSPs. The silicon version of the 'STA111 does
not support dedicated GPIO.
B
B
n
output appears to be a capacitive load.
n
: TRST
: Assertion of TRST
(0-n)
DD
B
is an input in the GPIO mode. The silicon version of
, TMS
B
= 0V (i.e.; not floating but tied to V
input has no pull-up resistor and no ESD clamp
, TDO
SS
n
) the input appears to be a capacitive load to
B
B
is an output on the LSP side of the 'STA111.
n
, and TRST
and TDO
(0-n)
pin will be driven high.
and TDI
DD
floating), the input appears to be a
n
B
n
are signals for enabling an exter-
B
will return the device back to its
pin will be driven low. In all other
(0-n)
inputs have a 25KΩ pull-up re-
are also dual purpose pins
DD
DD
n
and TDO
= 0V or floating), the
= 0V (i.e.; not floating
SS
) these inputs
n
are outputs,
B
.
DD
float-
21
contain both the stimulus (TDI
(TDO
The interpreter is able to parse the following commands:
ENDDR, ENDIR, RUNTEST, SDR, SIR, STATE, TRST.
PASS-THROUGH PINS
Each LSP may selectively have two pass-through pins. The
pair of pass-through pins consist of an input (A
put (Y
being received by the backplane pass-through input (A
Conversely, the level on the LSP pass-through input (A
drives the backplane pass-through output (Y
The Pass-through pins are available only when a single LSP
is selected. For each LSP these pins will be enabled when the
level 2 protocol state-machine is not in the Parked-TLR state.
When not enabled they are TRI-STATED.
LSP GATING
While the LSP state-machine (level 2 protocol) is in the
Parked-TLR state, the four LSP signals shall be controlled as
shown in
state (power-up, reset, PARKTLR or GOTOWAIT) a counter
in the LSP state-machine allows 512 TCK
occur on TCK
logic 0.
Letting 512 TCK
high TMS reset to occur on over 100 levels of hierarchy before
the 'STA111 gates TCK
clock system).
The 'STA111 does not require that any clock pulses are re-
ceived on TCK
Setting Bit 3 of Mode Register
Parked-RTI, Parked-Pause-DR and Parked-Pause-IR states.
Default is free-running (bit 3 = 0). The value stored in bit 3 of
Mode Register
pulses before gating TCK
section on Mode Register
IEEE 1149.4 SUPPORT
The 'STA111 provides support for a switched analog bus.
Each LSP has an unparked-TLR notification pin (LSP_AC-
TIVE
high (1) otherwise. This signal can be used to enable/disable
analog switches external to the 'STA111.
GPIO CONNECTIONS
General Purpose I/O (GPIO) pins are registered inputs and
outputs that are parameterized in the HDL. The two types of
GPIOs than can be used in the 'STA111 are described in the
next two sections. The silicon version of the 'STA111 supports
shared GPIO on all three available LSPs. The silicon version
of the 'STA111 does not support dedicated GPIO.
DEDICATED: Each LSP supports up to four (4) dedicated in-
puts and up to four (4) dedicated outputs. These are separate,
dedicated GPIO signals controlled by dedicated GPIO regis-
ters (one register per LSP). The GPIO outputs are updated
LSP
Connection
TDO
TMS
TDI
TCK
(0-2)
n
B
n
n
n
n
).
). The LSP pass-through output (Y
) which is low (0) when the LSP is in Parked-TLR and
Table 14
TABLE 14. Gated LSP Drive States
n
0
B
before gating. Once gated, TCK
Drive State
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
Pull-up resistor to provide a weak HIGH
TCK
does not effect the requirement of 512 clock
B
while in the Parked-TLR state.
pulses pass through to TCK
below. Upon entry into the Parked-TLR
B
for 512 pulses, then gated LOW
n
(for power saving in a free-running
0
).
n
in the Parked-TLR state. (See
0
to 1 gates TCK
B
) and expected response
n
B
) drives the level
B
clock pulses to
).
n
n
n
) and an out-
allows a five
n
www.national.com
when in the
will drive a
B
n
).
)