SCANSTA111SM National Semiconductor, SCANSTA111SM Datasheet - Page 16

• Manufacturer Part Number: SCANSTA111SM
• Manufacturer: National Semiconductor

Specifications of SCANSTA111SM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

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Register Descriptions
INSTRUCTION REGISTER: The instruction shift register is
an 8-bit register that is in series with the scan chain whenever
the TAP Controller of the SCANSTA111 is in the Shift-IR
state. Upon exiting the Capture-IR state, the value
XXXXXX01 is captured into the instruction register, where
XXXXXX represents the value on the S
'STA111 controller is in the Wait-For-Address state, the in-
struction register is used for 'STA111 selection via address
matching. In addressing individual 'STA111s, the chip's ad-
dressing logic performs a comparison between a statically-
configured (hard-wired) value on that 'STA111's slot inputs,
and an address which is scanned into the chip's instruction
register. Binary address codes 000000 through 111010 (00
through 3A Hex) are reserved for addressing individual
'STA111s. Address 3B Hex is for Broadcast mode.
During multi-cast (group) addressing, a scanned-in address
is compared against the (previously scanned-in) contents of
a 'STA111's Multi-Cast Group register. Binary address codes
111110 through 111111 (3A through 3F Hex) are reserved for
multi-cast addressing, and should not be assigned as
'STA111 slot-input values.
BOUNDARY-SCAN REGISTER: The boundary-scan regis-
ter is a sample only shift register containing cells from the S
(0-6)
ternal to the 'STA111. It permits the signals flowing between
the system pins to be sampled and examined without inter-
fering with the operation of the on-chip system logic.
The scan chain is arranged as follows:
TDI
BYPASS REGISTER: The bypass register is a 1-bit register
that operates as specified in IEEE Std. 1149.1 once the
'STA111 has been selected. The register provides a minimum
length serial path for the movement of test data between
TDI
test data register needs to be accessed during a board-level
test operation. Use of the bypass register shortens the serial
access-path to test data registers located in other compo-
nents on a board-level test data path.
MULTI-CAST GROUP REGISTER: Multi-cast is a method of
simultaneously communicating with more than one selected
B
B
and OE inputs. The register allows testing of circuitry ex-
→
and the LSPN. This path can be selected when no other
OE
→
S
6
→
S
5
→
S
4
→
FIGURE 10. Local Scan Port Synchronization from Parked-RTI State
S
3
→
S
2
→
S
(0-6)
1
→
S
inputs. When the
0
→
TDO
B
16
'STA111. The multi-cast group register (MCGR) is a 2-bit reg-
ister used to determine which multi-cast group a particular
'STA111 is assigned to. Four addresses are reserved for mul-
ti-cast addressing. When a 'STA111 is in the Wait-For-Ad-
dress state and receives a multi-cast address, and if that
'STA111's MCGR contains a matching value for that multi-
cast address, the 'STA111 becomes selected and is ready to
receive Level 2 Protocol (i.e., further instructions).
The MCGR is initialized to 00 upon entering the Test-Logic-
Reset state.
The following actions are used to perform multi-cast address-
ing:
1.
2.
MODE REGISTER
used primarily to configure the Local Scan Port Network.
Mode Register
ing the Test-Logic-Reset state. Bits 0, 1, 2, and 4 are used for
scan chain configuration as described in
UNPARK instruction is executed, the scan chain configura-
tion is as shown in
the scan chain configuration is TDI
TDO
MCGR Bits 1,0
00
01
10
11
TABLE 6. Multi-Cast Group Register Addressing
Assign all target 'STA111s to a multi-cast group by writing
each individual target 'STA111's MCGR with the same
multi-cast group code (see
step must be done by individually addressing each target
'STA111, using that chip's assigned slot value.
Scan out the multi-cast group address through the TDI
input of all 'STA111s. Note that this occurs in parallel,
resulting in the selection of only those 'STA111s whose
MCGR was previously programmed with the matching
multi-cast group code.
B
. Bit 3 is used for TCK
0
is initialized to 00000001 binary upon enter-
Table 7
0
: Mode Register
Hex Address
3C
3D
3E
3F
below. When all LSPs are parked,
n
configuration, see
Table
0
B
is an 8-bit data register
→
6). This configuration
Binary Address
00111100
00111101
00111110
00111111
'STA111-register
Table
7. When the
Table
8.
10124513
→
B