87016AYI IDT, Integrated Device Technology Inc, 87016AYI Datasheet - Page 2

• Manufacturer Part Number: 87016AYI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 87016AYI

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
13, 15, 17, 19
21, 23, 25, 27
29, 31, 33, 35
37, 39, 41, 43
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
12, 16, 20,
24, 28, 32,
36, 40, 44
Number
14, 18
22, 26
30, 34
38, 42
1, 48
10
11
45
46
47
2
3
4
5
6
7
8
9
QD3, QD2,
QC3, QC2,
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
QB3, QB2,
QA3, QA2,
QD1, QD0
QC1, QC0
CLK_ENA
CLK_ENB
CLK_ENC
CLK_END
QB1, QB0
QA1, QA0
CLK_SEL
MR/OE
V
V
V
V
Name
CLK0
CLK1
CLK1
GND
V
DDOD
DDOC
DDOB
DDOA
DD
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Description
Positive supply pins.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank D outputs. See Table 3.
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive
low. LVCMOS/LVTTL interface levels. See Table 3.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs to
high impedance. LVCMOS / LVTTL interface levels.
Power supply ground
Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank D output supply pins.
Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank C output supply pins.
Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank B output supply pins.
Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels.
Bank B output supply pins.
Clock select input. When HIGH, selects CLK1, CLK1 inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Inverting differential clock input.
Non-inverting differential clock input.
2
ICS87016AYI REV. C MAY 25, 2007