87016AYI IDT, Integrated Device Technology Inc, 87016AYI Datasheet

87016AYI

Manufacturer Part Number
87016AYI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of 87016AYI

Number Of Clock Inputs
2
Output Frequency
250MHz
Output Logic Level
LVCMOS/LVTTL
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Not Compliant
Block Diagram
LOW SKEW, 1-TO-16 LVCMOS/LVTTL
CLOCK GENERATOR
Description
÷2 frequency operation. Each bank also has its own power supply
pins so that the banks can operate at the following different
voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series or
parallel terminated transmission lines.
The divide select inputs, DIV_SELA:DIV_SELD, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The bank enable inputs,
CLK_ENA:CLK_END, support enabling and disabling each bank
of outputs individually. The CLK_ENA:CLK_END circuitry has a
synchronizer to prevent runt pulses when enabling or disabling the
clock outputs. The master reset input, MR/OE, resets the ÷1/÷2
flip flops and also controls the active and high impedance states of
all outputs. This pin has an internal pull-up resistor and is normally
used only for test purposes or in systems which use low power
modes.
The ICS87016I is characterized to operate with the core at 3.3V or
2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87016I
ideal for those clock applications demanding well-defined
performance and repeatability.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
DIV_SELD
DIV_SELC
HiPerClockS™
DIV_SELA
DIV_SELB
CLK_ENC
CLK_END
CLK_ENA
CLK_ENB
CLK_SEL
ICS
MR/OE
CLK0
CLK1
CLK1
The ICS87016I is a low skew, 1:16 LVCMOS/LVTTL
Clock Generator and is a member of the
HiPerClockS family of High Performance Clock
Solutions. The device has 4 banks of 4 outputs and
each bank can be independently selected for ÷1 or
0
1
÷1
÷2
1
0
1
0
1
0
1
0
D
LE
D
LE
D
LE
D
LE
4
4
4
4
QA0:QA3
QB0:QB3
QC0:QC3
QD0:QD3
1
Features
Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock
input
CLK1, CLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK0 supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Independent bank control for ÷1 or ÷2 operation
Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V
operation
Asynchronous clock enable/disable
Output skew: 170ps (maximum)
Bank skew: 50ps (maximum
Part-to-Part Skew: 800ps (maximum)
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
DIV_SELC
DIV_SELD
DIV_SELA
DIV_SELB
CLK_ENA
CLK_ENB
CLK_END
CLK_ENC
MR/OE
CLK0
GND
V
7mm x 7mm x 1.4mm package body
DD
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
48-Lead LQFP
ICS87016AYI REV. C MAY 25, 2007
Y Package
ICS87016I
Top View
ICS87016I
36
35
34
33
32
31
30
29
28
27
26
25
GND
QB0
V
QB1
GND
QB2
V
QB3
GND
QC0
V
QC1
DDOB
DDOB
DDOC

Related parts for 87016AYI

87016AYI Summary of contents

Page 1

... DIV_SELC DIV_SELD CLK_ENA D CLK_ENB 4 LE QC0:QC3 CLK_ENC CLK_END MR/ QD0:QD3 1 ICS87016I CLK0 GND ICS87016I 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS87016AYI REV. C MAY 25, 2007 GND 36 35 QB0 34 V DDOB 33 QB1 32 GND QB2 DDOB QB3 29 GND 28 QC0 DDOC QC1 25 ...

Page 2

... Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels. Bank B output supply pins. Clock select input. When HIGH, selects CLK1, CLK1 inputs. Pulldown When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. Pullup Inverting differential clock input. Pulldown Non-inverting differential clock input. 2 ICS87016AYI REV. C MAY 25, 2007 ...

Page 3

... Test Conditions 3.465V DD, DDOx 2.625V DD, DDOx V = 3.465V 2.625V DDOx V = 3.465V 1.89V DDOx V = 2.625V 1.89V DDOx V V DDOC, DDOD. Outputs Bank [A:D] Qx Frequency X Hi-Z N/A 0 Active fIN/2 1 Active fIN X LOW N/A 3 Minimum Typical Maximum ICS87016AYI REV. C MAY 25, 2007 Units pF Ω k Ω Ω ...

Page 4

... V = 2.5V ± 5%, 1.8V ± 5 DDOx Test Conditions Minimum 2.375 2.375 Typical Maximum 3.3 3.465 3.3 3.465 2.5 2.625 1.8 1.89 100 15 = -40°C to 85°C A Typical Maximum 2.5 2.625 2.5 2.625 1.8 1. ICS87016AYI REV. C MAY 25, 2007 = -40°C to Units Units ...

Page 5

... DD CLK1 V = 3.465V or 2.625V Minimum Typical 2 1.7 -0.3 -0.3 -5 -150 2.6 1.8 V – 0. Minimum Typical = 0V -150 0.15 GND + 0 0.3V. CLK1 DD ICS87016AYI REV. C MAY 25, 2007 Maximum Units 0.8 V 0.7 V 150 µA 5 µA µA µ 0.5 V 0.5 V 0.45 V µA 5 µA Maximum Units 5 µA 150 µ ...

Page 6

... Minimum Typical Maximum Units 2.8 3.4 2.75 3.4 200 45 40 /2. Minimum Typical Maximum 2.9 3.8 3.0 3.6 150 – 800 t Period Period ICS87016AYI REV. C MAY 25, 2007 250 MHz 3 170 ps 800 ps 700 /2. DDOX Units 250 MHz 4 ...

Page 7

... A Minimum Typical Maximum Units 2.9 3.5 3.0 3.5 200 45 40 /2. = -40°C to 85°C A Minimum Typical Maximum Units 3.0 3.9 3.0 3.9 200 45 40 ICS87016AYI REV. C MAY 25, 2007 250 MHz 4 170 ps 800 ps 700 ...

Page 8

... Measured on the Rising Edge 20% to 80% ƒ < 175MHz ƒ ≥ 175MHz /2 of the output. DDOX /2 of the output. DDOX DDOX 8 = -40°C to 85°C A Minimum Typical Maximum 3.1 4.1 3.0 3.9 150 45 40 /2. ICS87016AYI REV. C MAY 25, 2007 Units 250 MHz 5 210 ps 800 ps 700 ...

Page 9

... Core/2.5V LVCMOS Output Load AC Test Circuit 2.4V±0.9V 0.9V±5% SCOPE GND LVCMOS -0.9V±5% 3.3V Core/1.8V LVCMOS Output Load AC Test Circuit V DD SCOPE CLK1 Qx CLK1 GND Differential Input Level 9 Qx SCOPE DDO Qx V Cross Points PP ICS87016AYI REV. C MAY 25, 2007 SCOPE V CMR ...

Page 10

... Clock t Outputs R Output Rise/Fall Time IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR Part 1 Qx Part 2 Qy Part-to-Part Skew QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 Output Duty Cycle/Pulse Width/Period 80% 20 DDOX 2 V DDOX 2 tsk(pp) V DDOX PERIOD 100% odc = t PERIOD ICS87016AYI REV. C MAY 25, 2007 ...

Page 11

... A 1kΩ resistor can be used. IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR / Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input Outputs: LVCMOS Outputs: All unused LVCMOS output can be left floating. There should be no trace attached CLKx V_REF nCLKx C1 0. ICS87016AYI REV. C MAY 25, 2007 ...

Page 12

... Figure 2D. HiPerClockS CLK/CLK Input Driven by 3.3V 3. 125 125 CLK nCLK HiPerClockS Input 3. 50Ω 50Ω LVPECL Driven by a 3.3V LVPECL Driver 3. 50Ω 50Ω LVDS a 3.3V LVDS Driver ICS87016AYI REV. C MAY 25, 2007 3.3V CLK nCLK HiPerClockS Input 3.3V CLK R1 100 nCLK Receiver ...

Page 13

... NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS87016I is: 2034 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR θ vs. Air Flow JA 0 200 67.8°C/W 55.9°C/W 47.9°C/W 42.1°C/W 13 500 50.1°C/W 39.4°C/W ICS87016AYI REV. C MAY 25, 2007 ...

Page 14

... Ref. D3 & E3 2.0 e 0.5 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR -HD VERSION EXPOSED PAD DOWN Maximum 1.20 0.15 1.05 0.27 0.20 7.0 0.75 7° 0.08 14 ICS87016AYI REV. C MAY 25, 2007 ...

Page 15

... Shipping Packaging 48 Lead LQFP 48 Lead LQFP 1000 Tape & Reel “Lead-Free” 48 Lead LQFP “Lead-Free” 48 Lead LQFP 1000 Tape & Reel 15 Temperature Tray -40°C to 85°C -40°C to 85°C Tray -40°C to 85°C -40°C to 85°C ICS87016AYI REV. C MAY 25, 2007 ...

Page 16

... Test Circuit and 2.5V Core/1.8V Output Load Test Circuit diagrams. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Order/Part Number. 2.5V AC Characteristics Table - changed Output Duty Cycle test condition and limits. Added Output Pulse Width. 16 Date . 3/30/07 5/25/07 ICS87016AYI REV. C MAY 25, 2007 ...

Page 17

ICS87016I DIFFERENTIAL-TO-LVPECL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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