87016AYI IDT, Integrated Device Technology Inc, 87016AYI Datasheet - Page 11

• Manufacturer Part Number: 87016AYI
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 87016AYI

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
R2/R1 = 0.609.
Recommendations for Unused Input and Output Pins
Inputs:
CLK/CLK Inputs:
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
CLK Input:
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
ICS87016I
LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR
DD
= 3.3V, V_REF should be 1.25V and
DD
/2 is
11
Figure 1. Single-Ended Signal Driving Differential Input
Outputs:
LVCMOS Outputs:
All unused LVCMOS output can be left floating. There should be no
trace attached.
Single Ended Clock Input
C1
0.1u
V_REF
ICS87016AYI REV. C MAY 25, 2007
R1
1K
R2
1K
V
CC
CLKx
nCLKx