TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet - Page 5

• Manufacturer Part Number: TSEV83102G0BGL
• Manufacturer: E2V

Specifications of TSEV83102G0BGL

• Lead Free Status / RoHS Status: Not Compliant

Electrical Operating Characteristics (Continued)
V
voltage and performances are guaranteed within the limits of the specified V
V
clock inputs differential driven; analog-input single-ended driven.
2101D–BDC–06/04
Parameter
Analog input power level (50
Analog input capacitance (die)
Input leakage current
Input resistance
- single-ended
- differential
Clock Inputs
Logic common mode compatibility for clock inputs
Clock inputs common voltage range (V
(DC coupled clock input)
AC coupled for LVDS compatibility (common mode
1.2V)
Clock input power level (low-phase noise sinewave
input)
50
Clock input swing (single ended; with CLKB = 50
to GND)
Clock input swing (differential voltage) - on each
clock input
Clock input capacitance (die)
Clock input resistance
- single-ended
- differential ended
Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB, DRRB)
- logic low
- logic high
Digital Inputs (DRRB Only)
Logic Compatibility
- logic low
- logic high
CC
EE
= D
= 5V ; V
single-ended or 100
VEE
= -5V; V
PLUSD
= 0V (unless otherwise specified). ADC performances are independent of V
IN
- V
INB
differential
= 500 mVpp (full-scale single-ended or differential input);
single-ended)
CLK
or V
CLKB
)
Level
Test
4
4
4
4
4
4
4
4
4
4
4
4
Symbol
V
P
V
V
C
R
R
V
P
C
R
R
V
V
V
V
CLKB
I
CLK
CLK
CLK
CLK
CLK
CLK
IN
CM
IN
IH
IH
IN
IN
IN
IL
IL
-1.810
-1.165
Differential ECL to LVDS
±200
±141
PLUSD
Min
-1.2
49
98
45
90
-4
-5
-2
range (from -0.9V to 1.7V);
Negative ECL
±320
±226
Typ
100
100
0.3
0.3
- 2
10
50
50
0
0
PLUSD
TS83102G0B
common mode
-1.625
-0.880
±500
±354
Max
102
110
0.3
51
55
-3
4
0
dBm
dBm
Unit
mV
mV
pF
µA
pF
V
V
V
V
V
5