TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet
TSEV83102G0BGL
Specifications of TSEV83102G0BGL
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TSEV83102G0BGL Summary of contents
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... Pattern Generator Output (for Acquisition System Monitoring) • Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected) • CBGA 152 Cavity Down Hermetic Package • CBGA Package Evaluation Board TSEV83102G0BGL • Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0 Performance • 3.3 GHz Full Power Input Bandwidth (-3 dB) • ...
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Figure 1. Simplified Block Diagram VINB CLKB Functional Description The TS83102G0B is a 10-bit 2 Gsps ADC. The device includes a front-end master/slave Track and Hold stage (Sample and Hold), followed by an analog encoding stage (Analog Quantizer), which outputs ...
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Specification Absolute Maximum Ratings Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VIN and VINB Clock input voltage Maximum difference between ...
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Recommended Conditions of Use (Continued) Parameter Symbol Operating Temperature Range Storage Temperature Tstg Lead Temperature Tlead ADC performances are independent on V Note: 1. limits of the specified V Electrical Operating Characteristics (unless ...
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Electrical Operating Characteristics (Continued (unless otherwise specified). ADC performances are independent PLUSD voltage and performances are guaranteed within the limits of the specified -5V; V ...
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Electrical Operating Characteristics (Continued (unless otherwise specified). ADC performances are independent PLUSD voltage and performances are guaranteed within the limits of the specified -5V; V ...
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AC Electrical Characteristics at Ambient and Hot Temperatures (T Parameter AC Analog Inputs (1) Full power input bandwidth Small signal input bandwidth (10% full-scale) (2) Gain flatness (3) Input voltage standing wave ratio AC Performance: Nominal Condition at Ambient and ...
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AC Electrical Characteristics at Ambient and Hot Temperatures (T Parameter Total harmonic distortion Gsps Fin = 100 MHz Fs = 1.4 Gsps Fin = 700 MHz Fs = 1.4 Gsps Fin = 1950 MHz ...
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AC Performance at Cold Temperature (T Parameter AC Performance Condition -1 dBFS single-ended input mode; 50% clock duty cycle; 0 dBm differential clock (CLK, CLKB); binary output data format Signal-to-noise and distortion ratio Gsps Fin = 100 ...
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Transient and Switching Performances Parameter Transient Performance (1) Bit error rate ADC setting time ( 400 mVpp) IN INB Overvoltage recovery time ADC step response rise/fall time (10 - 90%) Overshoot Ringback Switching Performance and Characteristics (2) ...
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Table 1. Explanation of Test Levels Level Explanation 1 100% production tested at 25°C 2 100% production tested at 25°C 3 Sample tested only at specified temperatures 4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at ...
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Figure 2. Timing Diagram Regeneration Latches Note: TS83102G0B 12 N N+1 Analog input TA External clock Internal clock N N+1 Latch 1 N Latch 2 N Latch 3 Latch 4 Latch 5 Latch 6 Latch 7 Output Latches Latch 8 ...
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Table 2. Digital Coding Differential Analog Input Voltage Level > 250.25 mV >Top end of full-scale + ½ LSB 250.25 mV Top end of full-scale + ½ LSB 249.75 mV Top end of full-scale - ½ LSB 125.25 mV 3/4 ...
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TS83102G0B Package Description Table 4. Pin Description (CBGA 152) Symbol Pin Number Power Supplies K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8 CCTH B1, C1, D1, G1, M1, Q1, B2, C2, D2, ...
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Table 4. Pin Description (CBGA 152) (Continued) Symbol Pin Number DECB/DIODE A10 PGEB A9 DRRB SDA A6 SDAEN P1 2101D–BDC–06/04 TS83102G0B Function Decimation function enable or die junction temperature measurement: - Decimation active when connected to V ...
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Figure 3. Pinout Notes: TS83102G0B 16 OR ORB DIODE TS83102G0BM DECB/ PGEB CI-CGA 152 BOTTOM VIEW 1. To simplify PCB routing, the 4 NC balls can be electrically connected to the GND balls. 2. The pinout is shown from the ...
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Thermal and Moisture Characteristics Dissipation by Conduction and Convection The thermal resistance from junction to ambient RTH RTH JA conduction. The heat sink should be fixed in contact with the top side of the package (CuW heat spreader over Al2O3) ...
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Figure 4. Black Anodized Aluminium Heat Sink Glued on a Copper Base Screwed on Board (all dimensions in mm) 15 Circular Base (diam. 8.5 mm) 9 CuW Heat Spreader Tied AI203 Note: The cooling ...
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Typical Characterization Results Nominal Conditions V = 5V; 50% clock duty cycle; binary output data format wise specified. Typical Full Power Vin = -1 dBFS Input Bandwidth Gain flatness at ±0.15 dB from DC to 1.5 GHz Full ...
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Typical Step Tr measured = sqrt (Tr Response Tr PulseGenerator Actual Tr Figure 7. Step Response (Random Interleaved Sampling Method Measure) Figure 8. Zoom on Rise Time Step Response Note: TS83102G0B 20 2 PulseGenerator = 41 ps ...
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Typical Dynamic Figure 9. ENOB Versus Sampling Performances Versus Frequency in Nyquist Conditions Sampling Frequency (Fin = Fs/2) Figure 10. SFDR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) Figure 11. THD Versus Sampling Frequency in Nyquist Conditions (Fin ...
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Typical Dynamic Figure 13. ENOB Versus Input Performances Versus Frequency 1.4 Gsps Fin and Fs = 1.7 Gsps Figure 14. THD Versus Input Frequency 1.4 Gsps and Fs = 1.7 Gsps Figure 15. SFDR ...
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Typical Reconstructed The ADC input signal is sampled at a full sampling rate, but the output data times Signals and Signal decimated relax the acquisition system data rate consequence, the calculation ...
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Figure 19 1.7 Gsps and Fin = 898 MHz, -1 dBFS; Decimation Factor = 16, 32 kpoints FFT Figure 20 1.7 Gsps and Fin = 1699 MHz, -1 dBFS; Decimation Factor = 8, 32 kpoints FFT ...
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SFDR Performance Figure 22. SFDR (in dBC) With and Without Dither (-23 dBm MHz Out of Band with/without External Dither) Dither Fs = 1.4 Gsps and Fin = 710 MHz An increase in SFDR up to >10 ...
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Figure 24. Dual Tone Reconstructed Signal Spectrum 1.4 Gsps, Fin1 = 745 MHz, Fin2 = 755 MHz (-7 dBFS), IMD3 = 65 dBFS Note: Figure 25. Dual Tone Reconstructed Signal Spectrum 1.4 Gsps, Fin1 ...
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Figure 26. Dual Tone Reconstructed Signal Spectrum 1.4 Gsps, Fin1 = 1244 MHz, Fin2 = 1255 MHz (-7 dBFS), IMD3 = 65 dBFS Note: 2101D–BDC–06/ (FS/8) + Fin = 19 MHz F2 ...
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Typical Performance Sensitivity Versus Power Supply and Temperature Figure 27. ENOB Versus Junction Temperature (Fs = 1.4 Gsps, Fin = 698 MHz, -1 dBFS) Figure 28. SFDR Versus Junction Temperature (Fs = 1.4 Gsps, Fin = 698 MHz, -1 dBFS) ...
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Figure 30. ENOB Versus Figure 31. SFDR Versus Figure 32. SNR Versus 2101D–BDC–06/04 and 4.75V, 5V and 5.25V) EE 8.00 7.50 7.00 6.50 6.00 ...
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Considerations on ENOB: Linearity and Noise Contribution Figure 33. Example of a 16-kpoint FFT Computation 1.4 Gsps, Fin = 702 MHz, -1dBFS, T This is a 16384 points FFT times decimated since a DEMUX ...
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Without ADC input referred thermal noise: • ENOB = 9.2 bits • SINAD = 57 dB • THD = -55.7 dB (over 25 harmonics) • SFDR = -62.6 dBc • SNR = 57.3 dB Conclusion: Though the ENOB is 7.6 ...
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Equivalent Input/Output Schematics Figure 34. Equivalent Analog Input Circuit and ESD Protections 50 Controlled Transmission Line (Bonding + Package + Ball) VIN Package Pins Die Pads 50 Controlled VINB Transmission Line (Bonding + Package + Ball) Note: Figure 35. Equivalent ...
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Figure 36. Equivalent Data Output Buffer Circuit and ESD Protections Figure 37. ADC Gain Adjust Equivalent Input Circuits and Protections 2101D–BDC–06/04 VPLUSD ESD 100 fF 50 OUT - Pad ESD 130 VCC = 5V ESD 65 fF ...
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Figure 38. B/GB and PGEB Equivalent Input Schematics and ESD Protections Figure 39. DRRB Equivalent Input Schematics and ESD Protections TS83102G0B 34 GND ESD B/GB PAD ESD 130 250 VEE = -5V GND ...
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Definition of Terms Table 5. Definitions of Terms Term BER Bit Error Rate Full-power Input BW Bandwidth DG Differential Gain Differential Non- DNL linearity DP Differential Phase Maximum Sampling FS MAX Frequency Minimum Sampling FS MIN Frequency Full Power Input ...
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Table 5. Definitions of Terms (Continued) Power Supply PSRR Rejection Ratio Spurious Free SFDR Dynamic Range Signal to Noise and SINAD Distortion Ratio SNR Signal to Noise Ratio Small Signal Input SSBW Bandwidth TA Aperture Delay Encoding Clock TC Period ...
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TS83102G0B Operating Features Timing Information Timing Value for The timing values are defined in the “Electrical Operating Characteristics” on page 4. TS83102G0B The timing values are given at the package inputs/outputs, taking into account the package’s transmission line, bond wire, ...
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When used with Atmel’s TS81102G0 1:4/8 8/10 bit DMUX not necessary to initialize Data Ready, as this device can start on either clock edge. Principle of Data Ready Signal Control by DRRB Input Command Data Ready Output The ...
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Timing Diagram Figure 40. TS83102G0B Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at LOW Level INB CLK/CLKB TOD = 360 ps Digital Outputs TDR = 410 ps Data Ready DR/DRB Data Ready ...
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Analog Inputs (VIN/VINB) Static Issues: The ADC’s front-end Track and Hold differential preamplifier has been designed to be entered Differential Versus either in differential or single-ended mode the maximum operating speed of 2.2 Gsps, Single-ended (Full- without affecting ...
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Clock Inputs (CLK/CLKB) The TS83102G0B clock inputs are designed for either single-ended or differential operation. The device’s clock inputs are on-chip 100 tion mid point is AC coupled to ground through on-chip capacitor. Therefore, either ground or ...
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Equivalent Single- Figure 45. Single-ended Clock Inputs - Ground Common Mode ended Clock Input Voltage Levels (0 dBm Typical) Noise Immunity Information The circuit’s noise immunity performance begins at the design level. Efforts have been made on the design to ...
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See the recommended termination scenarios in Figures 46. and 47. below. Note: VPLUSD Digital Power • For differential ECL digital output levels: V Supply Settings connected to ground via a 5 • For the LVDS digital output logic compatibility: V ...
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LVDS Differential Figure 48. 50 Output Loading VPLUSD = 1.45V Configurations 50 Figure 49. Unterminated Differential Outputs (Optional) VPLUSD = 1.45V 50 LVDS Logic Figure 50. LVDS Format (Refer to the IEEE Standards 1596.3 - 1994): 1125 mV < Common ...
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Main Functions of the ADC Out-of-range Bit The out-of-range bit reaches a logical high state when the input exceeds the positive full-scale (OR/ORB) or falls below the negative full-scale. When the analog input exceeds the positive full-scale, the digital outputs ...
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When this function is active, the ADC outputs only 1 out of 32 bits of data, resulting in a data rate 32 times slower than the clock rate. Note: External Configuration Because of the use of one internal diode-mounted transistor ...
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Configuration 2: Note: Figure 53. Diode Pin Implementation of Die Junction Temperature Monitoring Function Only Junction Temperature The forward voltage drop (V Diode Transfer ture (including the chip’s parasitic resistance) is given in the following graph (I Function Figure 54. ...
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ADC Gain Control The ADC gain is adjustable by using pin R9 of the CBGA package. The gain adjust transfer function is shown below. Figure 55. Gain Adjust Transfer Function Sampling Delay Adjust The sampling delay adjust (SDA pin) enables ...
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... Control Line 17.40 mm Board Size : 12 holes on 44.0 mm square, diam 2.2 for heatsink mounting / centered on packaged device Note: For more details, refer to the TSEV83102G0BGL Evaluation Board datasheet. 2101D–BDC–06/04 150.00 mm GND GND GND GND GND GND GND ...
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... TS81102G0 (8/10-bit parallel channel 2 Gsps 1:4/1:8 demultiplexer). The ADC’s evaluation of static and dynamic performances can be done using the TSEV83102G0BGL ADC evaluation board, coupled with the TS81102G0 DMUX evaluation board and an acquisition system. The following block diagram shows a typical characterization set-up. ...
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Package Description Hermetic CBGA 152 Outline Dimensions Figure 59. Mechanical Description Bottom View Chamfer 0 Pin A1 Index (no ball) Ceramic body size : Ball pitch : 1.27 mm Cofired : Al2O3 Optional: ...
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Figure 60. Isometric View Figure 61. Package Top View TS83102G0B 52 21. 4.335 2.50 mm Marking Area 2 6.815 mm CuW 7 brazed on 9 metallization ...
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Figure 62. Package Top View with Optional Discrete Capacitors Note: 2101D–BDC–06/04 21. 4.335 2.50 mm Marking Area 2 6.815 mm CuW 7 brazed on 9 metalization ...
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Figure 63. Cross Section TS83102G0B 54 CBGA 152 21x21 mm Cross Section 10 bits/2 Gsps ADC. External heatsink required Al2O3 ceramic CuW Heat Spreader brazed on Al2O3 at VEE=-5 Volt potential Location for external heatsink 1.25 +/- 0.12 mm 0.65 ...
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... Ordering Information Part Number Package TS83102G0BCGL CBGA 152 TS83102G0BVGL CBGA 152 TSEV83102G0BGL CBGA 152 JTS83102G0-1V1B 2101D–BDC–06/04 Temperature Range “C” 0°C < <90° “V” -20°C < <110° Ambient Die Ambient TS83102G0B Screening Level Comments Standard product Standard product ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...