TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet - Page 48

• Manufacturer Part Number: TSEV83102G0BGL
• Manufacturer: E2V

Specifications of TSEV83102G0BGL

• Lead Free Status / RoHS Status: Not Compliant

ADC Gain Control
Sampling Delay Adjust
Figure 56. Typical Tuning Range (±120 ps for Applied Control Voltage Varying Between -0.5V and 0.5V on the SDA Pin)
48
TS83102G0B
400 p
300 p
200 p
100 p
-500 m
-400 m
The ADC gain is adjustable by using pin R9 of the CBGA package. The gain adjust transfer
function is shown below.
Figure 55. Gain Adjust Transfer Function
The sampling delay adjust (SDA pin) enables you to fine-tune the sampling ADC aperture
delay TAD around its nominal value (160 ps). This functionality is enabled with the SDAEN
signal, which is active when tied to V
This feature is particularly interesting for interleaving ADCs to increase the sampling rate.
The variation of the delay around its nominal value as a function of the SDA voltage is shown
in Figure 56 (simulation result).
-300 m
-200 m
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
-0.5
-100 m
Delay in the Variable Delay Cell at 60 C
-0.4
-0.3
SDA Voltage
0.00
EE
-0.2
and inactive when tied to GND.
V GA Gain Adjust Voltage (V)
-0.1
100 m
0
0.1
200 m
Typical
0.2
Min
300 m
0.3
0.4
400 m
0.5
2101D–BDC–06/04
500