TSEV83102G0BGL E2V, TSEV83102G0BGL Datasheet - Page 10

• Manufacturer Part Number: TSEV83102G0BGL
• Manufacturer: E2V

Specifications of TSEV83102G0BGL

• Lead Free Status / RoHS Status: Not Compliant

Transient and Switching Performances
Notes:
10
Parameter
Transient Performance
Bit error rate
ADC setting time (V
Overvoltage recovery time
ADC step response rise/fall time (10 - 90%)
Overshoot
Ringback
Switching Performance and Characteristics
Maximum clock frequency
Minimum clock frequency
Minimum clock pulse width (high)
Minimum clock pulse width (low)
Aperture delay
Aperture uncertainty
Output rise/fall time for DATA (20 - 80%)
Output rise/fall time for DATA READY (20 - 80%)
Data output delay
Data ready output delay
Output data to data ready propagation delay
Data ready to output data propagation delay
Output data pipeline delay
Data ready reset delay
1. Output error amplitude < ±6 LSB, Fs = 2 Gsps, T
2. See “Definition of Terms” on page 35.
3. 50 // C
4. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See “Propagation
5. Values for TD1 and TD2 are given for a 2 Gsps external clock frequency (50% duty cycle). For different sampling rates, apply
TS83102G0B
50 ps/pF (ECL). See “Timing Information” on page 37.
Time Considerations” on page 37.
the following formula: TD1 = T/2 + (|TOD - TDR|) and TD2 = T/2 + (|TOD - TDR|), where T = clock period. This places the ris-
ing edge (True/False) of the differential data ready signal in the middle of the output data valid window. This gives maximum
setup and hold times for external data acquisition.
(1)
(2)
(4)
LOAD
IN
(2)
- V
= 2 pF termination (for each single-ended output). Termination load parasitic capacitance derating value:
(4)
INB
(2)
(2)
= 400 mVpp)
(3)
(5)
(5)
(3)
Level
Test
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
J
= 110°C
Symbol
F
TR/TF
TR/TF
TRDR
F
minus
ITOD
TDRI
ORT
Jitter
BER
TOD
TDR
TPD
TC1
TC2
TD1
TD2
S
S
TS
TA
Max
Min
1000
Min
250
150
0.2
0.2
2
0
10
0.25
0.25
Typ
150
160
150
150
150
360
410
300
200
4.0
80
50
1
4
2
-12
Max
500
100
200
200
200
200
100
350
250
2.2
2.5
2.5
2101D–BDC–06/04
sample
fs rms
cycles
Error/
Clock
Gsps
Msps
Unit
ns
ps
ps
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%