72T6360L7-5BBI IDT, Integrated Device Technology Inc, 72T6360L7-5BBI Datasheet - Page 9

• Manufacturer Part Number: 72T6360L7-5BBI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72T6360L7-5BBI

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTIONS (Continued)
NOTE: 1. These pins should not change after master reset.
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
CONTROL AND FEATURE INTERFACE (Continued)
JSEL
MIC[2:0]
MCLK
MRS
MSPEED
MTYPE
[1:0]
PRS
TCK/
SCLK
TDI/SI
TDO/SO
TMS
Symbol
(1)
(1)
(1)
(1)
MTYPE0-R8
MIC2-U10 Memory
MIC1-R10 Configuration
MTYPE1-U8
MIC0-P10
Location
Pin No.
U11
R11
P11
P12
T10
H1
V5
T8
U6
Please see next page for Power & Ground pins and Pin Number Location Table.
JTAG Select
Master Clock
Master Reset
Memory Speed
Memory Type
[1:0]
Partial Reset
JTAG Clock/
Serial Clock
JTAG Test Data
Input/ Serial Input
JTAG Test Data
Output/Serial Output
JTAG Mode Select
Name
2.5V LVTTL the JTAG function is disabled and the JTAG pins will be used for serial programming of the
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL This includes the IDT Standard or FWFT mode timing, programmable flag settings, and
2.5V LVTTL of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
2.5V LVTTL operation, test data serially loaded via the TDI on the rising edge of TCK to the Instruction
2.5V LVTTL scan operation, test data serially loaded output via the TDO on the falling edge of TCK from
2.5V LVTTL if left unconnected.
OUTPUT
I/O TYPE
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
3.3V or
This pin selects whether the JTAG pins will be used for serial programming. If JSEL is
HIGH, the JTAG pins will only be used for JTAG boundary-scan function. If JSEL is LOW,
PAE/PAF offset registers.
These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations
for details.
33MHz reference clock used to generate CK and CK for external memory interface.
Master reset initializes the read and write pointers to zero and sets the output register to all
zeros. All initialized settings for the device will be configured during master reset.
This input select the speed of the external memory interfacing the sequential flow-control
device. A LOW selects 133MHz, and HIGH selects 166MHz.
These inputs select which type of external memory is interfacing the sequential flow-control
device. See Table 14 for the list of selectable memories.
Partial reset initializes the read and write pointers to zero and sets the output registers to all
zeros. All existing configurations in the sequential flow-control device will not be affected.
bus width and data rate mode.
This is a dual function pin. When the JSEL pin is HIGH, this is the clock input for JTAG boundary-
scan function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
of TCK and outputs change on the falling edge of TCK.
When the JSEL pin is LOW, this is the serial clock input for writing and reading the PAE/PAF
offset registers. On the rising edge of every SCLK when SWEN is LOW, one bit of data from
the SI pin is shifted into the PAE and PAF offset registers. On the rising edge of each SCLK when
SREN is LOW, one bit of data from the SO pin is shifted out of the PAE and PAF offset registers.
If the JTAG or serial programming is not used this signal needs to be tied to GND.
This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data input pin. One
Register, ID Register and Bypass Register.
When the JSEL pin is LOW, this is the serial input pin for the PAE/PAF offset registers. An
internal pull-up resistor forces TDI/SI HIGH if left unconnected.
This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data output pin.
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary
either the Instruction Register, ID Register and Bypass Register. This output is high-impedance
except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
When the JSEL pin is LOW, this is the serial data output pin for the PAE/PAF offset registers.
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS
directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH
of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009