72T6360L7-5BBI IDT, Integrated Device Technology Inc, 72T6360L7-5BBI Datasheet - Page 24

• Manufacturer Part Number: 72T6360L7-5BBI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72T6360L7-5BBI

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Not Compliant

write operations. Upon the completion of a valid read cycle, IR will go LOW
allowing a write to occur. The IR flag is updated by two WCLK cycles + t
after the valid RCLK cycle.
be held active.
READ STROBE AND READ CLOCK (RD/RCLK)
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR and
PAE flags will not be updated. The Write and Read Clocks can be independent
or coincident.
Data is asynchronously read from the SFC whenever there is a rising edge
on RD. In this mode the REN and RCS inputs must be tied LOW. The OE input
is used to provide asynchronous control of the three-state Qn outputs.
WRITE CHIP SELECT (WCS)
perform normal operations on the write port, the WCS must be enabled, held
LOW.
READ ENABLE (REN)
register on the rising edge of every RCLK cycle if the device is not empty.
then no new data is loaded into the output register. The data outputs Q
maintain the previous data value.
written to an empty cache, must be requested using REN provided that RCS
is LOW. When the last word has been read from the SFC, the Empty Flag (EF)
will go LOW, inhibiting further read operations. REN is ignored when the SFC
is empty. Once a write is performed, EF will go HIGH allowing a read to occur.
The EF flag is updated by two RCLK cycles + t
Both RCS and REN must be active, LOW for data to be read out on the rising
edge of RCLK.
to the outputs Q
after the first write. REN and RCS do not need to be asserted LOW for the First
Word to fall through to the output register. In order to access all other words, a
read must be executed using REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the SFC, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW;RCS = LOW), inhibiting
further read operations. REN is ignored when the SFC is empty.
be held active, (LOW).
OUTPUT ENABLE (OE)
data from the output register. When OE is HIGH, the output data bus (Q
into a high impedance state. During Master or a Partial Reset the OE is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further
WEN is ignored when the SFC is full in either FWFT or IDT Standard mode.
If asynchronous operation of the write port has been selected, then WEN must
If synchronous operation of the read port has been selected via ASYR, this
If asynchronous operation has been selected this input is RD (Read Strobe).
The WCS disables all Write data operations (data only) if it is held HIGH. To
When Read Enable is LOW, data is loaded from the RAM array into the output
When the REN input is HIGH, the output register holds the previous data and
In the IDT Standard mode, every word accessed at Q
In the FWFT mode, the first word written to an empty SFC automatically goes
If asynchronous operation of the Read port has been selected, then REN must
When Output Enable is enabled (LOW), the parallel output buffers receive
n
, on the third valid LOW-to-HIGH transition of RCLK + t
SKEW
after the valid WCLK cycle.
n
, including the first word
n
) goes
SKEW
SKEW
0
-Q
n
24
READ CHIP SELECT (RCS)
port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs
to go to the Low-Impedance state. When RCS goes HIGH, the next RCLK rising
edge causes the Qn outputs to return to HIGH Z. During a Master or Partial Reset
the RCS input has no effect on the Qn output bus, OE is the only input that provides
High-Impedance control of the Qn outputs. If OE is LOW the Qn data outputs will
be Low-Impedance regardless of RCS until the first rising edge of RCLK after
a Reset is complete. Then if RCS is HIGH the data outputs will go to High-
Impedance.
the first word is written to an empty SFC, the EF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
SFC will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user must take care when
a data word is written to an empty SFC in FWFT mode. If RCS is disabled when
an empty SFC is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take RCS active LOW to access this first word, place the output bus in LOW-Z.
REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.
A rising edge of RCLK with RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty SFC
when RCS is HIGH. See Figure 15 for Read Chip Select. If asynchronous
operation of the Read port has been selected, then RCS must be held active,
(tied LOW). OE provides three-state control of Qn.
BUS-MATCHING (BM[3:0])
Reset, the state of these pins is used to configure the device bus sizes. All flags
will operate on the word/byte size boundary as defined by the selection of bus
width. See Figures 22-25 for Bus-Matching Configurations. See Table 13, Bus-
Matching Configurations for the available configurations.
TABLE 13 – BUS-MATCHINGS
FLAG SELECT (FSEL[1:0])
programmable flags PAE and PAF. The selected value (listed in Table 14 -
MTYPE[1:0] Configurations) will apply to both PAE and PAF offset.
The Read Chip Select input provides synchronous control of the Read output
The RCS input does not effect the operation of the flags. For example, when
Also, when operating the SFC in FWFT mode the first word written to an empty
These pins are used to define the input and output bus widths. During Master
During master reset, these inputs will select one of four default values for the
BM3
1
1
1
1
1
0
0
0
0
BM2
0
0
1
0
1
0
1
0
1
BM1
0
0
0
1
1
0
0
1
1
COMMERCIAL AND INDUSTRIAL
BM0
0
1
1
1
1
1
1
1
1
TEMPERATURE RANGES
Read Bus
Width
x36
x18
x36
x36
x18
x18
FEBRUARY 10, 2009
x9
x9
x9
Write Bus
Width
x36
x36
x36
x18
x18
x18
x9
x9
x9