72T6360L7-5BBI IDT, Integrated Device Technology Inc, 72T6360L7-5BBI Datasheet - Page 3

• Manufacturer Part Number: 72T6360L7-5BBI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72T6360L7-5BBI

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Not Compliant

Figure 1. Sequential Flow-Control Device Block Diagram ............................................................................................................................................... 5
Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13
Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13
Figure 2c. Configuration 3 - Three Chip Solution ........................................................................................................................................................... 13
Figure 2d. Configuration 4 - Three Chip Solution ........................................................................................................................................................... 13
Figure 2e. Configuration 5 - Three Chip Solution ........................................................................................................................................................... 13
Figure 2f. Configuration 6 - Four Chip Solution .............................................................................................................................................................. 13
Figure 2g. Configuration 7 - Five Chip Solution .............................................................................................................................................................. 13
Figure 3. Memory Interface Connection (Single Chip) ................................................................................................................................................... 17
Figure 4. Memory Interface Connection (Two Chip) ...................................................................................................................................................... 17
Figure 5a. AC Test Load ................................................................................................................................................................................................ 29
Figure 5b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 29
Figure 6. Master Reset and Initialization ......................................................................................................................................................................... 32
Figure 7. Partial Reset ................................................................................................................................................................................................... 33
Figure 8. Write First Word Cycles - IDT Standard Mode ................................................................................................................................................. 34
Figure 9. Write First Word Cycles - FWFT Mode ............................................................................................................................................................ 34
Figure 10. Empty Boundary - IDT Standard Mode ........................................................................................................................................................ 35
Figure 11. Empty Boundary - FWFT Mode .................................................................................................................................................................... 35
Figure 12. Full Boundary - IDT Standard Mode ............................................................................................................................................................ 36
Figure 13. Full Boundary - FWFT Mode ....................................................................................................................................................................... 36
Figure 14. Output Enable ............................................................................................................................................................................................... 37
Figure 15. Read Chip Select ......................................................................................................................................................................................... 37
Figure 16. Write Chip Select .......................................................................................................................................................................................... 37
Figure 17. Bus-Matching Configuration - x36 In to x18 Out - IDT Standard Mode .......................................................................................................... 38
Figure 18. Bus-Matching Configuration - x36 In to x9 Out - IDT Standard Mode ............................................................................................................ 38
Figure 19. Bus-Matching Configuration - x18 In to x36 Out - IDT Standard Mode .......................................................................................................... 39
Figure 20. Bus-Matching Configuration - x9 In to x36 Out - IDT Standard Mode ............................................................................................................ 39
Figure 21. Synchronous PAE Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40
Figure 22. Synchronous PAF Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40
Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode ............................................................................................................................. 41
Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode .............................................................................................................................. 41
Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode .............................................................................................................................. 41
Figure 26. Asynchronous Empty Boundary - IDT Standard Mode .................................................................................................................................. 42
Figure 27. Asynchronous Full Boundary - IDT Standard Mode ...................................................................................................................................... 42
Figure 28. Asynchronous Read and PAE Flag - IDT Standard Mode ............................................................................................................................. 42
Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...................................................................................... 43
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes) ............................................................................................... 43
Figure 31. Standard JTAG Timing .................................................................................................................................................................................. 44
Figure 32. JTAG Architecture ......................................................................................................................................................................................... 45
Figure 33. TAP Controller State Diagram ....................................................................................................................................................................... 46
Figure 34. Depth Expansion Configuration in IDT Standard Mode ................................................................................................................................. 49
Figure 35. Depth Expansion Configuration in FWFT Mode ............................................................................................................................................ 49
Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode ....................................................................................................... 50
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
List of Figures
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009