72T6360L7-5BBI IDT, Integrated Device Technology Inc, 72T6360L7-5BBI Datasheet - Page 8

• Manufacturer Part Number: 72T6360L7-5BBI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72T6360L7-5BBI

• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTIONS (Continued)
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
WRITE PORT INTERFACE (Continued)
WCLK/WR
WCS
WEN
MEMORY INTERFACE
A[12:0]
BA[1:0]
CK
CK
CAS
DQ[63:0]
DQS[7:0]
RAS
WE
CONTROL AND FEATURE INTERFACE
BM[3:0]
FSEL[1:0]
FWFT
IDEM
IOSEL
Symbol
(1)
(1)
(1)
(1)
(1)
FSEL1-P6 Flag Select Bit
FSEL0-R6
BA0-C11 Address Input Bit
No. table
BA1-B11
No. table
No. table
No. table Strobe
Location
See Pin
See Pin
See Pin
See Pin
Pin No.
D12
A12
A11
V8
T7
V7
C7
A7
U7
R7
P7
Write Clock/
Write Strobe
Write Chip Select
Write Enable
Memory Address
Bus
Memory Bank
Memory Clock
Memory Clock
Inverted
Memory Column
Address Strobe
Memory Data Bus
Memory Data
Memory Row
Address Strobe
Memory Write
Enable
Bus-Matching Bit
First Word Fall
Through
IDT Standard Mode
Depth Expansion
Mode Select
I/O V
DDQ
Name
Select
Bi-Directional Input/output data bus for the external memory's data bus.
Bi-Directional Input/output data strobe to be connected to the external memory's data strobe.
2.5V LVTTL If asynchronous operation of the write port is selected, a rising edge on WR writes data into
2.5V LVTTL devices are sharing the same input data bus.
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL
2.5V LVTTL expansion interface. If depth expansion in FWFT mode is desired, this pin should be
2.5V LVTTL will be 3.3V tolerant. See table 15, for a list of affected I/O signals.
2.5V LVTTL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
SSTL_2
I/O TYPE
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
3.3V or
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
This is a dual function pin. If synchronous operation of the write port is selected, the rising
edge of WCLK writes data into the sequential flow-control device when WEN is enabled.
the sequential flow-control device without the need of a free-running input write clock.
Synchronous three-state control of the data inputs. Provides a means of controlling the
data inputs synchronous to WCLK. Typically used to avoid bus-contention when multiple
WEN enables WCLK for writing data into the sequential flow-control device. If
asynchronous mode is selected on the write port, this signal should be tied to GND.
Output address bus to be connected to the input address bus of the external memory to
provide row and column address.
Address bits to be connected to the external memory's BA inputs to determine which bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Clock output to be connected to the external memory's input clock.
Differential clock output to be connected to the external memory's differential input clock.
deactivate the column address strobe.
Output strobe signal to be connected to the external memory's RAS pin to activate and
deactivate the row address strobe.
Output strobe signal to be connected to the external memory's WE pin to activate and
deactivate the write address strobe.
Selects the bus width of the read and write ports.
During master reset, these inputs will select one of four default values for the programmable
flags PAE and PAF. The selected value will apply to both PAE and PAF offset.
During master reset, a HIGH on this input selects FWFT timing mode. A LOW selects IDT
Standard timing mode.
This select pin is used for depth expansion configuration in IDT Standard mode. If this pin
tied to GND. If no depth expansion is used, this pin should be tied to GND.
This input determines whether the inputs and outputs will tolerate a 2.5V or 3.3V voltage
signals. If IOSEL is HIGH, then all I/Os will be 2.5V tolerant. If IOSEL is LOW, then all I/Os
Output enable signal to be connected to the external memory's CAS pin to activate and
is tied HIGH, then the FF/IR signal will be inverted to provide a seamless depth
8
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009