72T6360L7-5BBI IDT, Integrated Device Technology Inc, 72T6360L7-5BBI Datasheet

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FEATURES • Product to be used with single or multiple external DDR SDRAM to provide significant storage capability 1Gb density • 166MHz operation (6ns read/write cycle time) • User selectable input and output port bus-sizing - x36in ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION Features ......................................................................................................................................................................................................................... 1 Description ...................................................................................................................................................................................................................... 4 Pin Configuration ............................................................................................................................................................................................................. 6 Pin Descriptions .......................................................................................................................................................................................................... 7-10 -Read Port Interface ............................................................................................................................................................................... 7 -Write Port Interface ................................................................................................................................................................................ 7 -Memory Interface .................................................................................................................................................................................. 8 -Control ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION Figure 1. Sequential Flow-Control Device Block Diagram ............................................................................................................................................... 5 Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13 Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION DESCRIPTION The IDT72T6360 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION Input D[35:0] 36 Register 36 Input Bus-Matching Logic 144 144 QP Cache optional 72 bypass 72 Error Check Bit Detection 72 Generator Correction optional bypass 72 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PIN CONFIGURATION A1 BALL PAD CORNER A GND GND DQ10 DQ8 DQ4 B GND GND DQS1 DQ9 DQ5 C DQ14 DQ13 DQ11 DQ12 DQ6 D DQ7 DQ16 DQ15 DQ17 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PIN DESCRIPTIONS Symbol Pin No. Name Location READ PORT INTERFACE ASYR (1) V6 Asynchronous Read Port EF/OR V13 Empty Flag/ Output Ready OE U12 Output Enable PAE U13 Programmable ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location WRITE PORT INTERFACE (Continued) WCLK/WR V8 Write Clock/ Write Strobe WCS T7 Write Chip Select WEN V7 Write Enable MEMORY INTERFACE ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location CONTROL AND FEATURE INTERFACE (Continued) (1) JSEL P11 JTAG Select MIC[2:0] (1) MIC2-U10 Memory MIC1-R10 Configuration MIC0-P10 MCLK H1 Master Clock ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PIN DESCRIPTIONS (Continued) Symbol Pin No. Name Location POWER AND GROUND SIGNALS V See Pin Core V and CC CC No. table Output voltage for DDR SDRAM AV B7, ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION DETAILED DESCRIPTIONS SEQUENTIAL FLOW-CONTROL STRUCTURE The IDT sequential flow-control (SFC) device is comprised of three inter- faces: input port, output port, and memory interface. The input and output port ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION EXTERNAL MEMORY CONFIGURATIONS The DDR SDRAM interface of the sequential flow-control (SFC) device has a 64-bit output data bus that provides up to four (16-bit SDRAM) external DDR SDRAM ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION CONNECTING THE DDR SDRAM Below are the various chipset solution configurations available to the sequential flow-control device (see Figure 2a-2g). The external memory interface is designed to seamlessly connect ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS Data Bus IDT 32 SFC Address Bus 12 CONFIGURATION 1 SFC Outputs DDR SDRAM DQ[31:0] DQ[31:0] DQS[3:0] DQS[3:0] A[11:0] A[11:0] ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued Data Bus IDT 256Mb 32 16 DDR SFC SDRAM Address Bus 13 6357 drw08 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION TABLE 4 – SFC TO DDR SDRAM INTERFACE CONNECTIONS(Continued) CONFIGURATION 7 SFC Outputs DDR SDRAM #1 DQ[15:0] DQ[15:0] DQ[31:16] -- DQ[47:32] -- DQ[63:48] -- DQS0 LDQS DQS1 UDQS DQS2 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION Sequential Flow-Control Device Sequential Flow-Control Device DQS[3:0] DQS[3: CAS CAS RAS RAS DQ[31:0] DQ[31:0] 32 A[11:0] A[11:0] 12 Figure 3. Memory Interface ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION TOTAL AVAILABLE MEMORY USAGE The sequential flow-control (SFC) is designed to efficiently use as much of the DDR SDRAM memory as possible, but due to the discontinuity between the ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION MAXIMUM I/O OPERATING FREQUENCY The sequential flow-control (SFC) device is designed to operate at the maximum frequency of 133MHz. There are certain configurations however, that can increase or decrease ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION ERROR DETECTION AND CORRECTION The Error Detection and Correction (EDC) feature is available to ensure data integrity between the DDR SDRAM interface and the SFC. The EDC corrects all ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION SETTING THE MEMORY INTERFACE SIGNALS The configurations listed in Figure 2a-2g can be programmed into the sequential flow-control device by using the MIC[2:0], MTYPE[1:0], and TABLE 9 – MEMORY ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION TABLE 10 – DEVICE CONFIGURATION Signal Pins Static State Configuration ASYR 0 Read port configured in asynchronous mode 1 Read port configured in synchronous mode ASYW 0 Write port ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION SIGNAL DESCRIPTIONS INPUTS DATA INPUTS ( Data inputs for 36-bit wide data ( data inputs for 18-bit wide data 0 35 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION MEMORY CONFIGURATION (MIC[2:0]) These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations for more information. MEMORY SPEED (MSPEED) This pin is used to determine ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the SFC is empty, EF will go ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG T Maximum Junction Temp. JMAX I DC Output Current OUT NOTES: 1. ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0°C to +70°C;Industrial I/O Type Symbol SFC Input I Input leakage current LI (LVTTL) V ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION 2.5V LVTTL AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 2.5V SSTL AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times ...

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... Industrial temperature range product for the 7.5ns speed grade is available as a standard device. All other speed grades are available by special order. ⎯ SYNCHRONOUS TIMING (1) = 2.5V ± 5 -40°C to +85° Commercial Com'l & Ind'l IDT72T6360L6 IDT72T6360L7-5 Min. Max. Min. — 166 — — ...

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... All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 7.5ns speed grade is available as a standard device. All other speed grades are available by special order. = 2.5V ± 5 -40°C to +85° Commercial Com'l & Ind'l IDT72T6360L6 IDT72T6360L7-5 Min. Max. Min. — 100 — 0.6 8 ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION MRS REN WEN SREN SWEN EF If IDT mode is selected OR If FWFT mode is selected FF If IDT mode is selected IR If FWFT mode is selected ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION PRS REN WEN SREN SWEN If IDT mode is selected FWFT mode is selected FF If IDT mode is selected IR If FWFT mode is selected ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WCLK t ENS WEN t ENS D[35:0] Word 0 RCLK REN EF Q[35:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION RCLK t t ENS ENH REN NO OPERATION t REF Q[35: (1) t SKEW1 WCLK t ENS WEN t DS Word 0 D[35:0] ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WCLK t ENS WEN D[35:0] W D-1 FF RCLK REN Q[35:0] Previous Word in Register NOTES: is the minimum time between a rising RCLK edge ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION RCLK REN t A Word 1 Word 2 Q[35:0] OE NOTE: 1. Settings: RCS = LOW, BM[3:0] = 1000, FWFT = LOW, ASYR = HIGH, and ASYW = HIGH. ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WCLK t ENS WEN t DS D[35:0] Word 0 RCLK REN EF Q[17:0] Previous Word in Register D[35:18] NOTES: is the minimum time between a rising WCLK edge and ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WCLK t ENS WEN t DS D[17:0] Word 0 Q[17:0] RCLK REN EF Q[35:0] NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WCLK t ENH WEN D[35:0] Word PAE n words or less in Memory words or less in Memory t ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION RD Q[35:0] Word PAF NOTES PAF offset, see Table10 for information on PAF offset values density of SFC. 2. ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WR D[35:0] RD Q[35:0] EF NOTES: 1. Settings LOW, RCS = LOW, WCS = LOW, FWFT = LOW, ASYR = LOW, and ASYW = LOW. 2. Asynchronous ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION SCLK t t SENS SWEN BIT 0 NOTES: 1. Settings: JSEL = LOW the required number of bits to program the PAE and ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION t 1 TCK t 3 TDI/ TMS t DS TDO SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO (1) Data Output Hold t DOH (1) Data ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION JTAG TIMING SPECIFICATIONS (IEEE 1149.1 COMPLIANT) The JTAG test port in this device is fully compliant with the IEEE Standard Test Access Port (IEEE 1149.1) specifications. Four additional pins ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION 1 Input is 0 TMS NOTES: 1. Five consecutive 1's at TMS will reset the TAP. 2. TAP controller resets automatically upon power-up. Refer to the IEEE Standard Test ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION THE INSTRUCTION REGISTER The instruction register (IR) is eight bits long and tells the device what instruction executed. Information contained in the instruction includes the mode ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION CLAMP The optional CLAMP instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the one- bit bypass register ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION DEPTH EXPANSION CONFIGURATION The sequential flow-control (SFC) device can be connected with multiple SFCs in depth expansion to provide additional storage density that’s greater than 1Gb. In depth expansion ...

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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x9, x18, x36 BIT WIDE CONFIGURATION WIDTH EXPANSION CONFIGURATION The sequential flow-control (SFC) device can be connected with another SFCs in width expansion to support bus-widths greater than 36-bits. This configuration connects the input and ...

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ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package DATASHEET DOCUMENT HISTORY 07/29/2004 pgs 7-11, 13-25, 27-43, 47, 49, and 51. 04/11/2005 pgs. 6 and 10. 06/28/2005 pg. 16. 10/10/2005 pgs. 1, 15, and 16. 02/10/2009 pg. ...