74SSTU32865BKG8 IDT, Integrated Device Technology Inc, 74SSTU32865BKG8 Datasheet - Page 9

• Manufacturer Part Number: 74SSTU32865BKG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTU32865BKG8

• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 270(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

TERMINAL FUNCTIONS
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
Re-Driven Outputs
Parity Error Output
Chip Select Inputs
Program Inputs
Ungated Inputs
Miscellaneous
Gated Inputs
Clock Inputs
Chip Select
Parity Input
Signal
Group
Inputs
DCKE0, DCKE1
DODT0, DODT1
QCKE0-1A, B
QODT0-1A, B
DCS0, DCS1
QCS0-1A, B
MCL, MCH
CSGateEN
Q0A:Q21A
Q0B:Q21B
CLK, CLK
Terminal
PTYERR
RESET
D0:D21
PARIN
Name
V
REF
1.8V LVCMOS
1.8V LVCMOS
0.9V nominal
Open Drain
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
SSTL_18
Type
Description
DRAM function pins not associated with Chip Select
DRAM inputs, re-driven only when Chip Select is LOW
DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at
least one will be LOW when a valid address/command is present. The register can be programmed
to re-drive all D-inputs only (CSGateEN HIGH) when at least one Chip Select input is LOW.
Outputs of the register, valid after the specified clock count and immediately following a rising edge
of the clock
Input parity is received on pin PARIN, and should maintain odd parity across the D0:D21 inputs, at the
rising edge of the clock
command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in
JEDEC definition).
Chip Select Gate Enable. When HIGH, the D0:D21 inputs will be latched only when at least one Chip
Select input is LOW during the rising edge of the clock. When LOW, the D0:D21 inputs will be latched
and redriven on every rising edge of the clock.
Differential master clock input pair to the register. The register operation is triggered by a rising edge on
the positive clock input (CLK).
Must be connected to a Logic LOW or HIGH.
Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR signal.
Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased
reliability.
When LOW, this output indicates that a parity error was identified associated with the address and/or
9
COMMERCIAL TEMPERATURE RANGE