74SSTU32865BKG8 IDT, Integrated Device Technology Inc, 74SSTU32865BKG8 Datasheet - Page 8

• Manufacturer Part Number: 74SSTU32865BKG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTU32865BKG8

• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Bits: 28
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 270(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
NOTES:
1. This parameter is not production tested.
2. Data and V
3. Data, V
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. The input and output negative voltage ratings may be exceeded if the ratings of the
3. This value is limited to 2.5V maximum.
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
Symbol
t
INACT (1,3)
t
f
ACT (1,2)
Symbol
CLOCK
V
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
I/P and O/P clamp current are observed.
t
V
tw
T
SU
t
V
V
H
O
I
I
I
I
STG
OK
(2,3)
DD
IK
DD
O
(2,3)
REF
, and clock inputs must be held at valid levels (not floating) a minimum time of t
REF
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup Time
Hold Time
Description
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current
Output Clamp Current V
Continuous Output Current,
V
Continuous Current through each
V
Storage Temperature Range
O
DD
inputs must be low a minimum time of t
= 0 to V
or GND
DD
DCSn before CLK↑, CLK↓
Data, PARIN, DODT, and DCKE before CLK↑, CLK↓
Data, DCSn, PARIN, DCKE, and DODT
after CLK↑, CLK↓
V
V
V
I
I
O
O
< 0
> V
< 0
> V
DD
DD
–0.5 to V
ACT
–65 to +150
–0.5 to 2.5
–0.5 to 2.5
max, after RESET is taken HIGH.
Max.
±100
±50
±50
±50
DD
+0.5
(1)
Unit
mA
mA
mA
mA
°C
V
V
V
8
INACT
max, after RESET is taken LOW.
Min.
0.7
0.5
0.5
—
—
—
1
V
DD
= 1.8V ± 0.1V
COMMERCIAL TEMPERATURE RANGE
Max.
270
—
10
15
—
—
—
MHz
Unit
ns
ns
ns
ns
ns