74SSTU32865BKG8 IDT, Integrated Device Technology Inc, 74SSTU32865BKG8 Datasheet - Page 14

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74SSTU32865BKG8

Manufacturer Part Number
74SSTU32865BKG8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 74SSTU32865BKG8

Logic Family
SSTU
Logical Function
Reg Bfr W/ParityTst
Number Of Elements
1
Number Of Bits
28
Number Of Inputs
28
Number Of Outputs
56
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
270(Min)MHz
Mounting
Surface Mount
Pin Count
160
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
NOTES:
1. C
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Z
TEST CIRCUITS AND WAVEFORMS (V
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
L
includes probe and jig capacitance.
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to RESET
Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with Respect to Clock Inputs)
Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to Clock Inputs)
Waveform 1
Waveform 2
Waveform 2
LVCMOS
Timing
Inputs
Timing
Output
Inputs
RESET
Output
Output
Input
DUT
Out
t
PLH
t
HL
V
V
t
ICR
HL
Load Circuit: High-to-Low Slew-Rate
ICR
C
V
V
L
DD
DD
0.15V
0.15V
= 10 pF
/2
/2
DD
V
14
V
ICR
ICR
V
= 1.8V ± 0.1V)
DD
Test Point
R
L
O
= 1KΩ
= 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
COMMERCIAL TEMPERATURE RANGE
V
V
I(PP)
V
V
V
V
V
0V
I(PP)
0V
0V
DD
OH
DD
OH
OL
RESET
RESET
RESET Input)
RESET

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