74SSTU32865BKG8 IDT, Integrated Device Technology Inc, 74SSTU32865BKG8 Datasheet

74SSTU32865BKG8

Manufacturer Part Number

74SSTU32865BKG8

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.74SSTU32865BKG8.pdf (15 pages)

Specifications of 74SSTU32865BKG8

Logic Family

SSTU

Logical Function

Reg Bfr W/ParityTst

Number Of Elements

Number Of Bits

Number Of Inputs

Number Of Outputs

High Level Output Current

-8mA

Low Level Output Current

8mA

Propagation Delay Time

3ns

Operating Supply Voltage (typ)

1.8V

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

270(Min)MHz

Mounting

Surface Mount

Pin Count

160

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / RoHS Status

Compliant

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FEATURES:

• 1.8V Operation

• SSTL_18 style clock and data inputs

• Differential CLK input

• Control inputs compatible with LVCMOS levels

• Flow-through architecture for optimum PCB design

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Available in 160-pin CTBGA package

COMMERCIAL TEMPERATURE RANGE

APPLICATIONS:

• Along with CSPU877/A/D DDR2 PLL, provides complete solution

• Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTU32865

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

machine model (C = 200pF, R = 0)

for DDR2 DIMMs

2005 Integrated Device Technology, Inc.

28-BIT 1:2 REGISTERED

BUFFER WITH PARITY

DESCRIPTION:

for 1.7V to 1.9V V

the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2

DIMM load.

are registered at the crossing of CLK going high and CLK going low.

(RESET) is low, the differential input receivers are disabled, and undriven

(floating) data, clock, and reference voltage (V

addition, when RESET is low all registers are reset, and all outputs are

forced low. The LVCMOS RESET and Cx inputs must always be held at

a valid logic high or low level.

been supplied, RESET must be held in the low state during power up.

asynchronous with respect to CLK and CLK. Therefore, no timing

relationship can be guaranteed between the two. When entering reset, the

to the time to disable the differential input receivers. However, when coming

out of a reset, the register will become active quickly, relative to the time to

enable the differential input receivers. As long as the data inputs are low,

and the clock is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the design of the

SSTU32865 must ensure that the outputs will remain low, thus ensuring no

glitches on the outputs.

outputs from changing states when both DCS0 and DCS1 are high. If either

DCS0 and DCS1 input is low, the Qn outputs will function normally. The

RESET input has priority over the DCS0 and DCS1 control and will force

the Qn outputs low and the PYTERR output high. If the DCS-control

functionality is not desired, then the CSGateEnable input can be hard-wired

to ground, in which case the set-up time requirement for DCS would be the

same as for the other D data inputs.

accepts a parity bit from the memory controller at its input pin PARIN,

compares it with the data received on the D-inputs, and indicates whether

a parity error has occured on its open-drain PYTERR pin (active low).

The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed

The SSTU32865 operates from a differential clock (CLK and CLK). Data

This device supports low-power standby operation. When the reset input

To ensure defined outputs from the register before a stable clock has

In the DDR2 DIMM application, RESET is specified to be completely

The device monitors both DCS0 and DCS1 inputs and will gate the Qn

The SSTU32865 includes a parity checking function. The SSTU32865

operation. All clock and data inputs are compatible with

COMMERCIAL TEMPERATURE RANGE

IDT74SSTU32865

REF

) inputs are allowed. In

APRIL 2005

DSC-6493/14

Related parts for 74SSTU32865BKG8

74SSTU32865BKG8 Summary of contents

Page 1

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FEATURES: • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds ...

Page 2

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FUNCTIONAL BLOCK DIAGRAM (1:2) V REF PARIN D0 D21 DCS0 CSGateEN DCS1 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CLK CLK COMMERCIAL TEMPERATURE RANGE (CS ACTIVE PARITY GENERATOR AND CHECKER 22 ...

Page 3

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY PIN CONFIGURATION REF D11 D9 G D18 D12 H CSGate D15 EN J CLK DCS0 ...

Page 4

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 160 BALL CTBGA PACKAGE ATTRIBUTES Top Mark TOP VIEW ...

Page 5

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FUNCTION TABLE (EACH FLIP-FLOP) (1) RESET DCS0 DCS1 ...

Page 6

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY PARITY AND STANDBY FUNCTION TABLE RESET DCS0 DCS1 ...

Page 7

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY REGISTER TIMING CLK CLK PARIN t PDM, t PDMSS Qn PTYERR PARITY LOGIC DIAGRAM PARIN CLOCK NOTE: 1. This ...

Page 8

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage Range DD (2,3) V Input Voltage Range I (2,3) V Output Voltage Range O I Input Clamp Current V < > ...

Page 9

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY TERMINAL FUNCTIONS Signal Terminal Group Name Ungated Inputs DCKE0, DCKE1 DODT0, DODT1 Chip Select D0:D21 Gated Inputs Chip Select Inputs DCS0, DCS1 Re-Driven Outputs Q0A:Q21A Q0B:Q21B QCS0-1A, B QCKE0-1A, B QODT0-1A, B Parity ...

Page 10

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Reference Voltage REF V Termination Voltage TT V Input Voltage High-Level Input Voltage Low-Level Input Voltage IL ...

Page 11

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) Symbol Parameter f MAX (2) t CLK and CLK to Q PDM t LOW to HIGH Delay, CLK and CLK to PYTERR LH ...

Page 12

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V CLK Inputs LVCMOS RESET Input t INACT I DD 10% Voltage and Current Waveforms Inputs Active and Inactive Times t W Input V ICR Voltage ...

Page 13

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V Output Output NOTES includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz 1.8V ...

Page 14

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY TEST CIRCUITS AND WAVEFORMS (V LVCMOS RESET Input Output Waveform 2 Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to RESET Timing Inputs Output Waveform 1 Voltage Waveforms: Open Drain Output ...

Page 15

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY ORDERING INFORMATION XX XXX IDT SSTU32 Temp. Range Device Type XX Package BKG Thin Profile, Fine Pitch, Ball Grid Array - Green 28-Bit 1:2 Registered Buffer with Parity 865 74 0°C to +70°C ...

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