PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 84

• Manufacturer Part Number: PNX1311EH/G
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G

• Lead Free Status / RoHS Status: Compliant

PNX1300/01/02/11 Data Book
the majority of instructions and data to the DSPCPU. The
wide paths to the caches are matched to the bandwidth
requirements of the DSPCPU.
Table 5-2. Summary of memory system
characteristics
To improve cache behavior and thus program perfor-
mance, the caches have a locking mechanism. In addi-
tion, the instruction cache is coupled with an instruction
decompression unit. The compressed instruction format
improves the cache hit rate and reduces the bus band-
width required between main memory and cache. In-
structions in main memory and cache use the com-
pressed format.
Figure 5-2. Formats of the DRAM_BASE and DRAM_LIMIT registers.
5-2
Branch units
Decompres-
sion unit
Instruction
cache
Memory units
Data cache
Data highway The on-chip data highway bus serves all on-
Main-memory
interface
SDRAM main
memory
MMIO_BASE
Unit
0x10 0000
0x10 0004
offset:
Branch units execute branch operations. Up
to three branch operations can be executed in
parallel, but the program must guarantee that
only one branch is taken.
Instructions are stored in memory and in the
instruction cache in a space-saving, com-
pressed format. The decompression unit
expands instructions to their full, 28-byte size
before they are issued to the CPU.
The instruction cache holds 32 KB, is 8-way
set-associative, and has a 64-byte block size.
A miss in a block causes the entire block to be
read from SDRAM. The cache can sustain an
issue rate of one instruction per cycle on
cache hits.
Memory units execute load and store opera-
tions. The data cache is dual ported to allow
the memory units to operate concurrently.
The data cache holds 16 KB, is 8-way set-
associative, has a 64-byte block size, and
implements a copyback, allocate-on-write pol-
icy. A miss in a block causes the entire block
to be read from SDRAM. The cache supports
memory-mapped I/O through non-cacheable
address regions.
chip units. The highway has separate 32-bit
data and address buses. Bus bandwidth is
allocated by the highway arbiter according to
one of several modes.
The main-memory interface contains the data-
highway access arbiter, the SDRAM control-
ler, and MMIO logic.
External SDRAM connects gluelessly to
PNX1300 over the 32-bit main-memory bus.
DRAM_BASE (r/w)
DRAM_LIMIT (r/w)
PRELIMINARY SPECIFICATION
Description
31
DRAM_BASE_FIELD
27
DRAM_LIMIT_FIELD
23
PNX1300’s processing units access the external
SDRAM through the on-chip central “data highway” bus.
The highway consists of separate 32-bit address and
data buses, and use of the bus is mediated by the main-
memory interface unit. The main-memory interface con-
tains the SDRAM controller and a central arbiter that de-
termines how much of the available SDRAM memory
bandwidth is allocated to each unit. Unused bandwidth is
always made available to the VLIW CPU for cache refill
and memory accesses that bypass the caches.
Table 5-2
nent of PNX1300’s memory system.
5.2
PNX1300 implements a 32-bit linear address space of
bytes. Within that address space, PNX1300 supports
several different apertures for specific purposes. The
DRAM aperture describes the part of the address space
into which the external SDRAM is mapped. SDRAM
must consist of a single, contiguous region of memory,
which is the most practical configuration for PNX1300
systems.
The location and size of the DRAM aperture is defined by
two registers, DRAM_BASE and DRAM_LIMIT. These
registers are both readable and writeable as MMIO reg-
isters and as PCI configuration space registers. The view
of the registers in MMIO space is shown in
The view of the registers in PCI configuration space is
described in
ation, the base address registers are assigned once dur-
ing boot and not changed when the DSPCPU is running.
Refer to
“System Boot,”
DRAM_LIMIT must be set equal to DRAM_BASE plus
the actual size of SDRAM present. The amount of the
SDRAM is not required to be a power of 2, but it must be
a multiple of 64 KB. Note that the size of the aperture as
set in the PCI configuration space can be larger, be-
cause it must be a power of 2.
A memory operation will access SDRAM if its address
satisfies:
Any address outside this range cannot access SDRAM.
When PNX1300 is reset, DRAM_BASE_FIELD is set to
0x0 and DRAM_LIMIT is set to 0x0010 0000 (1-MB
DRAM aperture starting at address 0x0). The boot pro-
cess described in
these initial settings.
[DRAM_BASE] ≤ address < [DRAM_LIMIT]
19
0
DRAM APERTURE
0
Chapter 11, “PCI Interface,”
gives a summary description of each compo-
0
Chapter 11, “PCI Interface.”
0
for a description of this process.
15
0
0
Chapter 13, “System Boot,”
0
0
0
0
0
0
11
0
0
Philips Semiconductors
0
0
0
0
0
0
0
0
7
0
0
and
0
0
In normal oper-
0
0
Chapter 13,
0
0
Figure
3
overrides
0
0
0
0
0
0
5-2.
0