PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 252

• Manufacturer Part Number: PNX1311EH/G
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G

• Lead Free Status / RoHS Status: Compliant

PNX1300/01/02/11 Data Book
Two types of data transfers are supported by the
PNX1300 I
• Data transfer from a master transmitter to a slave
• Data transfer from slave transmitter to master
The type of transaction is indicated by the LSbit of the ad-
dress byte. Data transfer from a master transmitter to a
slave receiver is called a WRITE. It is signified by a ‘0’ in
the LSbit of the address byte. Data transfer from a slave
transmitter to a master receiver is called a READ. It is
signified by a ‘1’ in the LSBit of the address byte.
Example steps for successful programming of the I
terface on PNX1300 are outlined as follows for both
reads and writes. Enable the I
tempting any accesses to external I
To enable the interface:
• Set bit IIC_CR.ENABLE (0x10340c) = 1
For write addressing mode:
1. On entry, clear any possible I
2. Enable desired I
16-6
Figure 16-4. START and STOP Conditions on I
receiver, also called a WRITE operation. The master
first transmits a 1-byte slave address, then the
desired number of data bytes. The slave receiver
returns an acknowledge bit after each byte. The mas-
ter terminates the transaction by a STOP after the
last byte.
receiver, also called a READ operation. The first byte
(the slave address) is transmitted by the master and
acknowledged by the slave. The selected slave
transmits successive data bytes which are each
acknowledged by the master, except the last byte
desired by the master, for which the master gener-
ates a ‘notack’ condition. This causes the slave to
terminate byte transmission. The slave transmitter
then must release the bus so that the master may
generate a STOP condition.
writing IIC_CR bits [25:22] = ‘1111’. (Note that pro-
grammers must mask and enable high-level interrupt
sources through the VIC facility in the DSPCPU. See
the appropriate PNX1300 databook chapter).
IIC_CR[31:28] bits appropriately.
SDA
SCL
2
C interface:
START
S
2
C interrupt sources by setting
PRELIMINARY SPECIFICATION
2
2
C interface prior to at-
C interrupt sources by
2
C devices.
STOP
P
2
2
C
C in-
3. Simultaneously load IIC_AR[31:25] with 7-bit slave
4. Load IIC_DR[31:0] with data for the write. Note that
5. Detect I
6. If transfer count is not yet fulfilled, clear GDI and FI
For read addressing mode:
1. On entry, clear any possible I
2. Enable desired I
3. Simultaneously load IIC_AR[31:25] with 7-bit slave
4. Detect I
5. Clear GDI and FI bits and read the contents of
6. Proceed with step iv) until all data is read, i.e byte-
16.6.1
If a slave device does not generate an ACK where re-
quired, this is considered a NAK. Upon receipt of a NAK
after transmitting a device address or data byte, the mas-
ter takes the following actions:
• the I
• a STOP condition is issued on the bus
• no more data is sent
address, IIC_AR.DIRECTION = 0 and IIC_AR[15:8]
with the appropriate bytecount for the transfer.
writing this register triggers the transfer across the I
bus.Up to 4 bytes will be transferred after writing, de-
pendent on bytecount in IIC_AR[8:15}.Transfers of
more than 4 bytes have to be done by breaking them
down into a sequence of 4-byte transfers and a last
transfer which may be less than 4 bytes. This is done
by repeatedly reloading the register until the byte-
count is fulfilled. Transfer is done high byte first, pro-
ceeding to low byte.
and respond - OR - Detect I
respond. (Note that this last step is dependent upon
system software requirements).
bits and proceed with step iv) until all data is written.
writing IIC_CR bits [25:22] = ‘1111’. (Note that pro-
grammers must mask and enable high level interrupt
sources through the VIC facility in the DSPCPU. See
the appropriate databook chapter).
IIC_CR[31:28] bits appropriately.
address, IIC_AR.DIRECTION = 1 and IIC_AR[15:8]
with the appropriate bytecount for the transfer. Note
that writing this register triggers the read across the
I
respond - OR - Detect I
(Note that this last step is dependent upon system
software requirements.)
IIC_DR. Up to 4 bytes will be available in IIC_DR, fe-
ver if the remaining bytecount was less than 4. Bytes
are stored high byte first, proceeding to low byte.
count is fulfilled.
2
C bus.
2
C state becomes IDLE (STATE = 000)
Slave NAK
2
2
C resulting condition code in IIC_SR[31:28]
C resulting condition in IIC_SR[31:28] and
2
C interrupt sources by setting
2
Philips Semiconductors
C interrupt and respond.
2
C high level interrupt and
2
C interrupt sources by
2
C