PNX1311EH/G NXP Semiconductors, PNX1311EH/G Datasheet - Page 518

• Manufacturer Part Number: PNX1311EH/G
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G

• Lead Free Status / RoHS Status: Compliant

PNX1300/01/02/11 Data Book
Table C-1. Little Endian data format in PNX1300 DSPCPU register, highway, SDRAM memory, PCI bus, host
memory, host CPU register
C.3
The following test can be used to verify the correct oper-
ation of PNX1300 in Little Endian and Big Endian sys-
tems.
1. Store a 32-bit constant ‘0x04050607’ from the host
2. Store a 32-bit constant ‘0x04050607’ from the host
C.4
The endian-ness handling in each PNX1300 unit is de-
scribed in the following sections. Most units use the high-
way/PCI bus to transfer data. The highway/PCI bus has
four byte lanes. The bit assignment of the highway/PCI
bus lanes is shown in
Table C-2. Bit assignment of the highway/PCI bus
lanes
The PCI bus and PNX1300 highway buses are address-
invariant buses, i.e the data corresponding to address
offset ‘0’ uses the byte-0 lane of the highway/PCI bus,
the data corresponds to address offset ‘1’ uses the byte-
1 lane of the highway/PCI bus etc.
C-2
PCSW-
value
BSX
CPU to the PNX1300 SDRAM through the PCI inter-
face. Load the word from the same address to one of
the PNX1300’s global register and check for the same
value.
CPU to the PNX1300 SDRAM through PCI interface.
Load a byte from the same address to one of the
PNX1300 global registers. Check for the value of
‘0x04’ in Big Endian systems, and check for the value
‘0x07’ in Little Endian systems.
1
1
1
1
1
1
1
Bits
TEST TO VERIFY THE CORRECT
OPERATION OF PNX1300 IN BIG AND
LITTLE ENDIAN SYSTEMS
REQUIREMENT FOR THE PNX1300 TO
OPERATE IN EITHER LITTLE ENDIAN
OR BIG ENDIAN MODE
Endian
Mode
Little
Little
Little
Little
Little
Little
Little
byte 3
31:24
Data Transaction
Byte read/write
Byte read/write
Byte read/write
Byte read/write
Half-Word r/w
Half-Word r/w
Table
PRELIMINARY SPECIFICATION
Word r/w
byte 2
23:16
type
C-2.
byte 1
15:8
00001000
00001000
00001002
00001000
00001001
00001002
00001003
Address
byte 0
7:0
msb
01020304
xxxx0304
DSPCPU
xxxx0304
xxxxxx04
xxxxxx04
xxxxxx04
xxxxxx04
register
Data in
lsb
C.4.1
The PNX1300 PCSW register has a byte-sex (BSX) bit
to configure the PNX1300 in Big Endian or Little Endian
mode.
mode as defined in
This BSX bit is used by the PNX1300 data cache unit for
the store/load operation. Data cache performs three cat-
egories of data transactions:
• Read/write data from/to DSPCPU registers to/from
• Read/write of MMIO data from/to DSPCPU registers
• Read/write data from/to DSPCPU registers to/from
The DSPCPU endian-ness is determined by the value of
the BSX bit in the PCSW register.
C-3
the data cache to transfer the data to/from DSPCPU reg-
ister to/from data cache or SDRAM.
C-3
DRAM_BASE and DRAM_LIMIT range.
There is no byte-swap required for the MMIO data trans-
action from/to DSPCPU register to the MMIO registers.
However, one of the special registers, PCI_DATA, does
not follow the normal MMIO transactions. The data
cache byte-swaps the data to/from the PCI_DATA regis-
ter using the data translation format as defined in
C-1
For the PCI configuration cycle and I/O cycle transac-
tions from the DSPCPU, a programmer can byte-swap
the data in the DSPCPU registers and write to the
PCI_DATA register using MMIO write operations. There
is no byte-swap from the PCI_DATA register in BIU unit
to the PCI bus. Software uses the
3
fore writing the data to the PCI_DATA register for the
configuration and I/O cycle transactions.
data to byte-swap the data within the CPU register be-
data cache or SDRAM
to/from MMIO registers
PCI address space through special registers in the
BIU unit.
and
describe the data translation format being used by
Dcache/SDRAM/
Data in highway/
byte3
[31:24]
are restricted to addresses that fall in the
01020304
xxxx0304
0304xxxx
xxxxxx04
xxxx04xx
xx04xxxx
04xxxxxx
PCI-bus
Table C-3
This bit must be set to ‘1’ for the Little Endian
Data Cache
byte0
[7:0]
for the memory cycle.
Chapter 3, “DSPCPU Architecture.”
CPU register
Data in host
msb
01020304
xxxx0304
xxxx0304
xxxxxx04
xxxxxx04
xxxxxx04
xxxxxx04
Philips Semiconductors
lsb
Table C-1
Table C-1
Table C-1
byte3
[31:24]
Data in host
01020304
xxxx0304
0304xxxx
xxxxxx04
xxxx04xx
xx04xxxx
04xxxxxx
memory
or
and
and
Table C-
byte0
[7:0]
Table
Table
Table