ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 593
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ALXD800EEXJ2VC C3
Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VC_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VC C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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GeodeLink™ PCI Bridge Register Descriptions
6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:44
43:32
31:12
11:9
Bit
7:6
8
5
4
3
2
1
0
Name
TOP
RSVD (RO)
BASE
RSVD (RO)
EN
RSVD (RO)
PF
WC
RSVD (RO)
WP
DD
CD
5000201Dh
R/W
00000000_00000000h
Description
Top of Region. 4 KB granularity, inclusive.
Reserved (Read Only). Reserved for future use.
Base of Region. 4 KB granularity, inclusive.
Reserved (Read Only). Reserved for future use.
Region Enable. Set to 1 to enable access to this region.
Reserved (Read Only). Reserved for future use.
Prefetchable. Reads to this region have no side-effects.
Write Combine. Writes to this region may be combined.
Reserved (Read Only). Reserved for future use.
Write Protect. When set to 1, only read accesses are allowed. Write accesses are
ignored (master abort).
Discard Data. When set to 1, write access are accepted and discarded. Read accesses
are ignored (master abort).
Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to
0, accesses are marked as coherent.
BASE
TOP
GLPCI_R5 Bit Descriptions
GLPCI_R5 Register Map
RSVD
9
8
33234H
RSVD
7
RSVD
6
5
4
3
2
1
593
0
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