ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 232
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ALXD800EEXJ2VC C3
Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VC_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VC C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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6.2.2.12 Performance Counters (MC_CFPERF_CNT1)
MSR Address
Type
Reset Value
232
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
Bit
2:0
31:0
Bit
Name
WR2DAT
Name
CNT0
CNT1
2000001Bh
RO
00000000_00000000h
33234H
Description
Counter 0. Performance counter 0. Counts the occurrence of events at the GLIU inter-
face. Events are specified in CNT0_DATA (MSR 2000001Ch[7:0]). Reset and stop con-
trol on this counter is done via MSR 200001Ch[33:32]. (Default = 0h)
Counter 1. Performance counter 1. Counts the occurrence of events at the GLIU inter-
face. Events are specified in CNT1_DATA (MSR 2000001Ch[23:16]. Reset and stop con-
trol on this counter is done via MSR 200001Ch[35:34]. (Default = 0h)
Description
Write Command To Data Latency. Number of clocks between the write command
and the first data beat. Valid values are: [2,1,0], and must correspond to the installed
DIMMs as follows:
0h: No delay.
1h: 1-clock delay for DDR unbuffered DIMMs. (Default)
MC_CFPERF_CNT1 Bit Descriptions
MC_CF1017_DATA Bit Descriptions
MC_CFPERF_CNT1 Register Map
CNT1
CNT0
GeodeLink™ Memory Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0
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