ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 584

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PBUS)
MSR Address
Type
Reset Value
The PBUS model specific register is used to control the way that the GLPCI module generates (or does not generate) PCI
configuration cycles onto the PCI bus. SEC (bits [39:32]) should be configured with the PCI bus number for the locally
attached PCI bus. SUB (bits [55:48]) should be configured with the PCI bus number for the highest numbered PCI bus that
is accessible via the PCI interface. DEV (bits [31:0]) should be configured to indicate which device numbers will NOT gener-
ate PCI configuration cycles on the PCI bus.
6.16.2.4 GLPCI Debug Packet Configuration (GLPCI_DEBUG)
MSR Address
Type
Reset Value
Control relay of debug packets to PCI. The functionality that this register controls has been removed from the GLIU. There-
fore this register is obsolete.
6.16.2.5 GLPCI Fixed Region Enables (GLPCI_REN)
MSR Address
Type
Reset Value
584
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:56
55:48
47:40
39:32
31:0
Bit
RSVD
Name
RSVD (RO)
SUB
RSVD (RO)
SEC
DEV
RSVD
50002012h
R/W
00FF0000_00000000h
50002013h
R/W
00000000_00000000h
50002014h
R/W
00000000_00000000h
33234H
Description
Reserved (Read Only). Reserved for future use.
Subordinate Bus Number. Specifies the subordinate PCI bus number for all PCI buses
reachable via the PCI interface.
Reserved (Read Only). Reserved for future use.
Secondary Bus Number. Specifies the secondary PCI bus number for the PCI interface.
Device Bitmap. Specifies the virtualized PCI devices. Each bit position corresponds to a
device number. A 0 instructs the GLPCI to allow PCI configuration cycles for the device
to be generated on the PCI bus. A 1 tells the GLPCI to virtualize the device by generating
an SSMI instead of a PCI configuration cycle.
GLPCI_PBUS Bit Descriptions
SUB
GLPCI_PBUS Register Map
GLPCI_REN Register Map
Spare
DEV
RSVD
GeodeLink™ PCI Bridge Register Descriptions
AMD Geode™ LX Processors Data Book
9
9
8
8
7
7
6
6
5
5
4
4
SEC
3
3
2
2
1
1
0
0