ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 136

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)
MSR Address
Type
Reset Value
DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information
about debug conditions that have occurred. DR7 contains debug condition enables, types, and lengths. The contents of
debug registers are more easily accessed using the MOV instruction.
136
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LEN3 TYPE3 LEN2 TYPE2 LEN1 TYPE1 LEN0 TYPE0 RSVD GD
39, 38
37, 36
35, 34
33, 32
63:62
61:60
59:58
57:56
55:54
53:52
51:50
49:48
47:46
44:40
31:16
12:4
Bit
45
15
14
13
3
2
1
0
Name
LEN3
TYPE3
LEN2
TYPE2
LEN1
TYPE1
LEN0
TYPE0
RSVD
GD
RSVD
G3, L3
G2, L2
G1, L1
G0, L0
RSVD
BT
BS
BD
RSVD
B3
B2
B1
B0
00001343h
R/W
00000000_FFFF0000h
33234H
RSVD (FFFFh)
Description
Breakpoint 3 Length.
Breakpoint 3 Type.
Breakpoint 2 Length.
Breakpoint 2 Type.
Breakpoint 1 Length.
Breakpoint 1 Type.
Breakpoint 0 Length.
Breakpoint 0 Type.
Reserved.
Enable Global Detect Faults.
Reserved.
Breakpoint 3 Enables.
Breakpoint 2 Enables.
Breakpoint 1 Enables.
Breakpoint 0 Enables.
Reserved.
TSS T-Bit Trap Occured.
Single-Step Trap Occured.
Global Detect Fault Occured.
Reserved.
Breakpoint 3 Matched.
Breakpoint 2 Matched.
Breakpoint 1 Matched.
Breakpoint 0 Matched.
DR7_DR6_MSR Bit Descriptions
DR7_DR6_MSR Register Map
BT BS BD
RSVD
AMD Geode™ LX Processors Data Book
RSVD (FFh)
9
8
CPU Core Register Descriptions
G3 L3 G2 L2 G1 L1 G0 L0
7
6
5
4
B3 B2 B1 B0
3
2
1
0