ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 314

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

6.6.3.2
DC Memory Offset 004h
Type
Reset Value
This register contains general control bits for the DC. Unless otherwise noted in the bit descriptions table, settings written to
this register do not take effect until the start of the following frame or interlaced field.
314
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
31
30
29
28
27
26
25
DC General Configuration (DC_GENERAL_CFG)
Name
DBUG
DBSL
CFRW
DIAG
CRC_MODE
SGFR
SGRE
R/W
00000000h
33234H
Description
Debug Mode. Effective immediately.
0: Disable
1: Enable.
Debug Select. Effective immediately.
0: FIFO control signals transmitted to debug port.
1: Memory control signals transmitted to debug port.
Compressed Line Buffer Read/Write Select. Effective immediately.
Only has effect if in DIAG mode (bit 28 = 1).
0: Write address enabled to Compressed Line Buffer (CLB) in diagnostic mode.
1: Read address enabled to CLB in diagnostic mode.
RAM Diagnostic Mode. Effective immediately.
0: Normal operation.
1: RAM diagnostic mode. This bit allows testability of the on-chip Display FIFO and CLB
CRC Mode. Effective immediately.
This bit selects the CRC algorithm used to compute the signature.
0: nxt_crc[23:0] <= {crc[22:0], (crc[23], crc[3], crc[2])} ^ data[23:0].
1: nxt_crc = (reset) ? 32’h01 :( {crc[30:0], 1’b0} ^ ((crc[31]) ? 32’h04c11db7 : 0) )^ data.
Signature Free Run. Effective immediately.
0: Capture display signature for one frame.
1: Capture display signature continuously for multiple frames.
When this bit is cleared, the signature accumulation stops at the end of the current frame.
Signature Read Enable. Effective immediately.
0: Reads to DC_PAL_DATA (DC Memory Offset 074h[23:0]) return palette data.
1: Reads to DC_PAL_DATA (DC Memory Offset 074h[23:0]) return signature data. The
via the diagnostic access registers. A low to high transition resets the Display FIFO
and Compressed Line Buffer read and write pointers.
palette address register contents are ignored in this case. Note that the automatic pal-
ette address increment mechanism will still operate even though the address is
ignored.
DC_GENERAL_CFG Bit Descriptions
DC_GENERAL_CFG Register Map
DFHPEL
DFHPSL
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
6
5
4
3
2
1
0