ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 228

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

228
34:32
31:30
29:28
23:8
Bit
7:4
36
35
27
26
25
24
3
Name
D0_CB
RSVD
D0_PSZ
RSVD
MSR_BA
RST_DLL
EMR_QFC
EMR_DRV
EMR_DLL
REF_INT
REF_STAG
REF_TST
33234H
Description
DIMM0 Component Banks. Number of component banks per module bank for DIMM0.
0: 2 Component banks. (Default)
1: 4 Component banks.
Reserved.
DIMM0 Page Size.
000: 1 KB
001: 2 KB
010: 4 KB
011: 8 KB
Reserved.
Mode Register Set Bank Address. These are the bank select bits used for program-
ming the DDR DIMM’s Extended Mode Register. These bits select whether the GLMC is
programming the Mode Register or the Extended Mode Register.
00: Program the DIMM Mode Register. (Default)
01: Program the DIMM Extended Mode Register. Bits [26:24] determine the program
10: Reserved.
11: Reserved.
Mode Register Reset DLL. This bit represents A8 in the Mode Register, which when set
to 1 resets the DLL as part of the DIMM initialization sequence. JEDEC recommends
clearing this bit back to 0 on the final load-mode-register command before activating any
bank.
0: Do not reset DLL. (Default.
1: Reset DLL.
Extended Mode Register FET Control. This bit programs the DIMM’s QFC# signal. The
QFC# signal provides control for FET switches that are used to isolate module loads from
the system memory busy at times when the given module is not being accessed. Only
pertains to x4 configurations.
0: Enable. (Default)
1: Disable.
Extended Mode Register Drive Strength Control. This bit selects either normal or
reduced drive strength.
0: Normal. (Default)
1: Reduced.
Extended Mode Register DLL. This bit disables/enables the DLL.
0: Enable. (Default)
1: Disable.
Refresh Interval. This field determines the number of SDRAM clocks between refresh.
This value multiplied by 16 is the average number of clocks between refresh. The default
value, 00h, disables refresh.
Refresh Staggering. This field controls the number of clocks (0-16) between REF com-
mands to different banks during refresh cycles. Staggering is used to help reduce power
spikes during refresh. Note that with a setting of 0, no staggering occurs, so all module
banks are refreshed simultaneously. (Default = 1)
Test Refresh. This bit, when set high, generates one refresh request that the GLMC
queues in its refresh request queue. Since the refresh queue is 8-deep, 8 sets/clears of
this bit queues 8 refresh requests, thus forcing a refresh request out to DRAM. This bit
should only be used for initialization and test. (Default = 0)
MC_CF07_DATA Bit Descriptions (Continued)
data.
100: 16 KB
101: 32 KB
110: Reserved
111: DIMM0 Not Installed (Default)
GeodeLink™ Memory Controller Register Descriptions
AMD Geode™ LX Processors Data Book