ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 329

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Display Controller Register Descriptions
6.6.5.2
DC Memory Offset 044h
Type
Reset Value
This register contains CRT horizontal blank timing information.
Note: A minimum of 32 pixel clocks is required for the horizontal blanking portion of a line in order for the timing generator
6.6.5.3
DC Memory Offset 048h
Type
Reset Value
This register contains CRT horizontal sync timing information. Note however, that this register should also be programmed
appropriately for flat panel only display, since the horizontal sync transition determines when to advance the vertical
counter.
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
27:16
15:12
31:28
27:16
11:0
Bit
Bit
RSVD
RSVD
to function correctly.
DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING)
DC CRT Horizontal Sync Timing (DC_H_SYNC_TIMING)
Name
RSVD
H_BLK_END
RSVD
H_BLK_START
Name
RSVD
H_SYNC_END
R/W
xxxxxxxxh
R/W
xxxxxxxxh
H_SYNC_END
Description
Reserved. These bits should be programmed to zero.
Horizontal Blank End. This field represents the pixel clock count at which the horizontal
blanking signal becomes inactive minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
Reserved. These bits should be programmed to zero.
Horizontal Blank Start. This field represents the pixel clock count at which the horizon-
tal blanking signal becomes active minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
Description
Reserved. These bits should be programmed to zero.
Horizontal Sync End. This field represents the pixel clock count at which the CRT hori-
zontal sync signal becomes inactive minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
The horizontal sync must be at least 8 pixels in width.
H_BLK_END
DC_H_BLANK_TIMING Bit Descriptions
DC_H_SYNC_TIMING Bit Descriptions
DC_H_BLANK_TIMING Register Map
DC_H_SYNC_TIMING Register Map
RSVD
RSVD
9
9
8
8
33234H
H_BLK_START
7
7
H_SYNC_ST
6
6
5
5
4
4
3
3
2
2
1
1
329
0
0