LSISAS1064 LSI, LSISAS1064 Datasheet - Page 96

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

4-28
Register: 0xXX
PCI-X Next Pointer
Read Only
Register: 0xXX
PCI-X Command
Read/Write
Table 4.4
PCI Host Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Bits [6:4]
Encoding
0b000
0b001
0b010
15
0
7
x
0
0
x
Maximum Outstanding Split Transactions
PCI-X Next Capabilities Pointer
This register points to the next item in the device’s
capabilities list. The value of this register varies according
to system configuration.
1
Reserved
This field is reserved.
Maximum Outstanding Split Transactions
These bits indicate the maximum number of split
transactions the LSISAS1064 can have outstanding at
one time. The LSISAS1064 uses the most recent value
of this register each time it prepares a new sequence.
Note that if the LSISAS1064 prepares a sequence before
the setting of this field changes, the PCI function initiates
the prepared sequence with the previous setting.
Table 4.4
Maximum Outstanding
0
Split Transactions
x
0
provides the bit encodings for this field.
PCI-X Next Pointer
0
PCI-X Command
1
2
3
x
8
0
7
0
x
1
1
x
0
0
x
0
0
[15:7]
0
x
[7:0]
[6:4]
0
0