LSISAS1064 LSI, LSISAS1064 Datasheet - Page 51

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.8
Multi-ICE Test Interface
Include a 20-pin header to access the ARM Multi-ICE signals through the
ICE JTAG post. The header has a 100 mil spacing between posts. The
connector is a 20-way header that mates with IDC sockets that are
mounted on a ribbon cable. This header enables LSI Logic to debug the
board design.
to include a header, route the ARM Multi-ICE signals to through-holes.
LSI Logic considers access to the ARM Multi-ICE signals essential
to all board designs.
Include pull-up resistors on the signals that require a pull-up
(TRST_ICE/, TDI_ICE, TMS_ICE, TCK_ICE) and on pin 15. In addition,
include GND and VDD_33.
Table 2.3
1. Connect a 4.7 k
Multi-ICE Test Interface
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Does not support 5-bit and 6-bit characters
Does not support 1.5 stop bits
Provides additional registers to support the speed sense logic
Provides a synchronous interface to allow access to internal registers
and FIFOs
Pin
11
13
15
17
19
1
3
5
7
9
ARM Multi-ICE Header Pinout
Table 2.3
resistor between this pin and 3.3 V.
VDD (3.3 V)
TRST_ICE/
RTCK_ICE
TMS_ICE
TCK_ICE
TDI_ICE
TDO_ICE
Signal
provides the header pinout. If it is not possible
NC
NC
NC
1
1
1
1
1
Pin
10
12
14
16
18
20
2
4
6
8
VDD (3.3 V)
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2-25