LSISAS1064 LSI, LSISAS1064 Datasheet - Page 30

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.1.1.1
2.1.1.2
2.1.1.3
2-4
PCI/PCI-X Interface
System Interface
IOP
The LSISAS1064 provides a PCI-X interface that supports up to a 64-bit,
133 MHz PCI-X bus. The LSISAS1064 PCI interface is backward
compatible with previous implementations of the PCI specification, with
the exception that the LSISAS1064 does not support 5 V PCI. For more
information on the PCI interface, refer to
Description.”
In combination with the IOP, the system interface supports the
Fusion-MPT architecture. The system interface efficiently passes
messages between the LSISAS1064 and the host using a high-
performance, packetized mailbox architecture. The LSISAS1064 system
interface coalesces PCI interrupts to minimize traffic on the PCI bus and
maximize system performance. The system interface contains five
hardware FIFOs for the message queuing lists: Request Free FIFO,
Request Post FIFO, Reply Free FIFO, Reply Post FIFO, and High Priority
Request FIFO. The LSISAS1064 contains control logic for the FIFOs,
while the messages are stored in the context RAM or in external
memory.
All host accesses to the IOP, external memory, and timer and
configuration subsystems pass through the system interface and use the
primary bus. The host system initiates data transactions on the primary
bus with the system interface registers. PCI Memory Space [0] and the
PCI I/O Base Address registers identify the location of the system
interface register set.
provides a bit level description of the system interface register set.
The LSISAS1064 I/O processor controls the system interface and
manages the host side of the Fusion-MPT architecture without host
processor intervention, which frees the host processor for other tasks.
The LSISAS1064 I/O processor (IOP) is a 32-bit ARM926 RISC
processor that provides instruction and data requests to streamline
operations and increase performance.
Functional Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Chapter 4, “PCI Host Register Description,”
Section 2.3, “PCI Functional