LSISAS1064 LSI, LSISAS1064 Datasheet - Page 102

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

4-34
31
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register: 0x00
System Doorbell
Read/Write
The System Doorbell register is a simple message passing mechanism
that allows the system to pass single word messages to the embedded
IOP processor and vice versa.
When a host system PCI master writes to the Host Registers->Doorbell
register, the LSISAS1064 generates a maskable interrupt to the IOP. The
value written by the host system is available for the IOP to read in the
System Interface Registers->Doorbell register. The IOP clears the
interrupt status after reading the value.
Conversely, when the IOP processor writes to the System Interface
Registers->Doorbell register, the LSISAS1064 generates a maskable
interrupt to the PCI system. The host system can read the value written
by the IOP in the Host Registers->Doorbell register. The host system
clears the interrupt status bit and interrupt pin by writing any value to the
Host Registers->Interrupt Status register.
Register: 0x04
Write Sequence
Read/Write
The Write Sequence register provides a protection mechanism against
inadvertent writes to the
PCI Host Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
0
0
0
0
0
0
0
0
0
0
Host Doorbell Value
During a write, this register contains the doorbell value
that the host system passes to the IOP. During a read,
this register contains the doorbell value that the IOP
passes to the host system.
0
0
0
0
System Doorbell
Write Sequence
0
0
16 15
16 15
0
0
Host Diagnostic
0
0
0
0
0
0
0
0
0
0
0
0
register.
0
0
8
0
8
0
7
0
7
0
0
0
0
0
0
0
0
1
0
0
[31:0]
0
1
0
0
0
1