ISP1183BS STEricsson, ISP1183BS Datasheet - Page 62

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

23. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Summary of EOT conditions for a bulk
Table 11. Recommended EOT usage for isochronous
Table 12. Summary of control bits . . . . . . . . . . . . . . . . . .23
Table 13. Command and register overview . . . . . . . . . . .24
Table 14. Endpoint Configuration register: bit allocation .27
Table 15. Endpoint Configuration register: bit
Table 16. Address register: bit allocation . . . . . . . . . . . .27
Table 17. Address register: bit description . . . . . . . . . . .27
Table 18. Mode register: bit allocation . . . . . . . . . . . . . . .28
Table 19. Mode register: bit description . . . . . . . . . . . . .28
Table 20. Hardware Configuration register: bit allocation 29
Table 21. Hardware Configuration register: bit
Table 22. Interrupt Enable register: bit allocation . . . . . .30
Table 23. Interrupt Enable register: bit description . . . . .30
Table 24. Endpoint FIFO organization . . . . . . . . . . . . . . .32
Table 25. Example of endpoint FIFO access . . . . . . . . . .32
Table 26. Endpoint Status register: bit allocation . . . . . . .32
Table 27. Endpoint Status register: bit description . . . . .33
Table 28. Endpoint Status Image register: bit allocation .34
Table 29. Endpoint Status Image register: bit description 34
Table 30. DMA Function and Scratch register: bit
Table 31. DMA Function and Scratch register: bit
Table 32. DMA Configuration register: bit allocation . . . .36
Table 33. DMA Configuration register: bit description . . .36
Table 34. DMA Counter register: bit allocation . . . . . . . .37
Table 35. DMA Counter register: bit description . . . . . . .37
Table 36. Error Code register: bit allocation . . . . . . . . . .37
Table 37. Error Code register: bit description . . . . . . . . .37
Table 38. Transaction error codes . . . . . . . . . . . . . . . . . .38
Table 39. Lock register: bit allocation . . . . . . . . . . . . . . .38
Table 40. Lock register: bit description . . . . . . . . . . . . . .39
Table 41. Frame Number register: bit allocation . . . . . . .39
Table 42. Frame Number register: bit description . . . . . .39
Table 43. Example of Frame Number register access . .39
Table 44. Chip ID register: bit allocation . . . . . . . . . . . . .40
Table 45. Chip ID register: bit description . . . . . . . . . . . .40
Table 46. Interrupt register: bit allocation . . . . . . . . . . . .40
Table 47. Interrupt register: bit description . . . . . . . . . . .41
Table 48. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 49. Recommended operating conditions . . . . . . . .42
Table 50. Static characteristics: supply pins . . . . . . . . . .43
ISP1183_3
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
ISP1183 operation modes . . . . . . . . . . . . . . . . .8
Endpoint access and programmability . . . . . . .13
Programmable FIFO size . . . . . . . . . . . . . . . . .14
Memory configuration example . . . . . . . . . . . .14
Endpoint selection for the DMA transfer . . . . .16
8237 compatible mode: pin functions . . . . . . .17
DACK-only mode: pin functions . . . . . . . . . . . .18
endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Rev. 03 — 20 January 2009
Table 51. Static characteristics: digital pins . . . . . . . . . . 43
Table 52. Static characteristics: analog I/O pins DP
Table 53. Dynamic characteristics . . . . . . . . . . . . . . . . . 45
Table 54. Dynamic characteristics: analog I/O pins DP
Table 55. Dynamic characteristics: parallel interface
Table 56. Dynamic characteristics: access cycle timing . 47
Table 57. Dynamic characteristics: single-cycle DMA
Table 58. Dynamic characteristics: burst mode DMA
Table 59. SnPb eutectic process (from J-STD-020C) . . . 57
Table 60. Lead-free process (from J-STD-020C) . . . . . . 57
Table 61. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 62. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 60
Low-power USB Peripheral Controller with DMA
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
© ST-NXP Wireless 2009. All rights reserved.
ISP1183
61 of 65