ISP1183BS STEricsson, ISP1183BS Datasheet - Page 28

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 14.
[1]
[2]
Table 16.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reset value of the control OUT endpoint is fixed as 83h for the Endpoint Configuration register.
The reset value of the control IN endpoint is fixed as C3h for the Endpoint Configuration register.
[1][2]
Endpoint Configuration register: bit allocation
Address register: bit allocation
12.1.2 Address register (R/W: B7h/B6h)
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
Code: 30h to 3Fh — read (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte
Table 15.
This command sets the USB assigned address in the Address register and enables the
USB device. The Address register bit allocation is shown in
A USB bus reset sets the device address to 00h (internally) and enables the device. The
value of the Address register (accessible by the microcontroller) is not altered by the bus
reset. In response to the standard USB request (Set Address), firmware must issue a
Write Device Address command, followed by sending an empty packet to the host. The
new device address is activated when the host acknowledges the empty packet.
Code: B6h/B7h — write or read Address register
Transaction — write or read 1 byte
Table 17.
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0] This field specifies the FIFO size according to
Endpoint Configuration register: bit description
Address register: bit description
Symbol
DEVEN
DEVADR[6:0]
DBLBUF
R/W
R/W
5
0
5
0
Description
Logic 1 indicates an enabled FIFO with allocated memory. Logic 0 indicates
a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN). It also determines
the DMA transfer direction (0 = read, 1 = write).
Logic 1 indicates that this endpoint has double buffering.
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or
interrupt endpoint.
Rev. 03 — 20 January 2009
Description
Logic 1 enables the device.
This field specifies the USB device address.
FFOISO
R/W
R/W
4
0
4
0
Low-power USB Peripheral Controller with DMA
DEVADR[6:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
FFOSZ[3:0]
Table
Table
16.
© ST-NXP Wireless 2009. All rights reserved.
5.
R/W
R/W
1
0
1
0
ISP1183
R/W
R/W
0
0
0
0
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