ISP1183BS STEricsson, ISP1183BS Datasheet - Page 35

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 28.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Endpoint Status Image register: bit allocation
12.2.5 Clear Endpoint Buffer (70h, 72h to 7Fh)
12.2.6 Check Endpoint Status (D0h to DFh)
EPSTAL
R
7
0
Code: 61h to 6Fh — validate endpoint buffer (control IN, endpoints 1 to 14)
Transaction — none
This command unlocks and clears the buffer of the selected OUT endpoint, allowing the
reception of new packets. Reception of a complete packet causes the Buffer Full flag of an
OUT endpoint to be set. Any subsequent packets are refused by returning a NAK
condition, until the buffer is unlocked using this command. For a double-buffered
endpoint, this command switches the current FIFO for CPU access.
Remark: For special aspects of the control OUT endpoint, see
Code: 70h, 72h to 7Fh — clear endpoint buffer (control OUT, endpoints 1 to 14)
Transaction — none
This command checks the status of the selected endpoint FIFO without clearing any
status or interrupt bits. The command accesses the Endpoint Status Image register, which
contains a copy of the Endpoint Status register. The bit allocation of the Endpoint Status
Image register is shown in
Code: D0h to DFh — check status (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte
Table 29.
Bit
7
6
5
4
3
EPFULL1
R
6
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
Endpoint Status Image register: bit description
EPFULL0
R
5
0
Rev. 03 — 20 January 2009
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 =
not stalled).
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA0 PID, 1 =
DATA1 PID).
This bit is set by hardware. Logic 1 indicates that a new set-up packet
has overwritten the previous set-up information, before it was
acknowledged or before the endpoint was stalled. This bit is cleared by
reading, if writing the set-up data has finished.
Firmware must check this bit before sending an Acknowledge Setup
command or stalling the endpoint. On reading logic 1, firmware must stop
ongoing set-up actions and wait for a new set-up packet.
Table
DATA_PID
R
4
0
28.
Low-power USB Peripheral Controller with DMA
WRITE
OVER
R
3
0
SETUPT
R
2
0
Section
CPUBUF
© ST-NXP Wireless 2009. All rights reserved.
R
1
0
9.5.
ISP1183
reserved
R
0
0
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