ISP1183BS STEricsson, ISP1183BS Datasheet - Page 48

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 56.
V
ISP1183_3
Product data sheet
Symbol
Write command + write data (see
T
T
Fig 13. Parallel interface read timing
Fig 14. Parallel interface write timing
BUS
cy(WC-WD)
cy(WD-WD)
(1) If required, CS_N can be kept permanently asserted. There is no need to de-assert and assert in between the read and
(1) If required, CS_N can be kept permanently asserted. There is no need to de-assert and assert in between the read and
= V
REG(3V3)
write cycles.
write cycles.
WR_N
CS_N
DATA
Dynamic characteristics: access cycle timing
RD_N
CS_N
DATA
A0
16.1.2 Access cycle timing
Parameter
cycle time for write command, then write data
cycle time for write data
A0
= 2.7 V to 3.9 V; V
t
SLWL
t
t
SLRL
RLDV
t
DVWH
t
AVRL
t
WLWH
t
AVWL
t
RLRH
DD(I/O)
Figure 15
t
RHAX
= 1.8 V; unless otherwise specified.
t
t
WHSH
WHAX
t
WHDZ
t
and
RHSH
t
WHWL
t
RHDZ
Rev. 03 — 20 January 2009
t
RHRL
Figure
(1)
(1)
16)
Conditions
C
Low-power USB Peripheral Controller with DMA
L
= 30 pF
[1]
Min
100
90
Typ
-
-
© ST-NXP Wireless 2009. All rights reserved.
004aaa256
004aaa257
ISP1183
Max
-
-
Unit
ns
ns
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