ISP1183BS STEricsson, ISP1183BS Datasheet - Page 36

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 30.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Function and Scratch register: bit allocation
12.2.7 Acknowledge Setup (F4h)
12.3.1 DMA Function and Scratch register (R/W: B3h/B2h)
DMAEN
12.3 DMA commands
R/W
R/W
15
0
7
0
Table 29.
This command acknowledges to the host that a SETUP packet was received. The arrival
of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the
control IN and OUT endpoints. The microcontroller needs to re-enable these commands
by sending an Acknowledge Setup command, see
Code: F4h — acknowledge setup
Transaction — none
This command accesses the 16-bit DMA Function and Scratch register, which can be
used by firmware to save and restore information. For example, the device status before
powering down in the suspend state. The register bit allocation is given in
Code: B2h/B3h — write or read DMA Function and Scratch register
Transaction — write or read 2 bytes
Table 31.
Bit
2
1
0
Bit
15
14 to 13
12 to 8
7 to 0
R/W
R/W
14
0
6
0
Symbol
SETUPT
CPUBUF
-
reserved
Endpoint Status Image register: bit description
DMA Function and Scratch register: bit description
Symbol
DMAEN
-
SFIRH[4:0]
SFIRL[7:0]
R/W
R/W
13
0
5
0
Rev. 03 — 20 January 2009
Description
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer, 1 = secondary buffer).
reserved
Description
Writing logic 1 enables DMA function.
reserved; must be logic 0
Scratch Information register (high byte)
Scratch Information register (low byte)
R/W
R/W
12
0
4
0
SFIRL[7:0]
Low-power USB Peripheral Controller with DMA
R/W
R/W
11
0
3
0
Section
SFIRH[4:0]
R/W
R/W
…continued
10
0
2
0
9.5.
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
9
0
1
0
ISP1183
Table
30.
R/W
R/W
8
0
0
0
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