ISP1183BS STEricsson, ISP1183BS Datasheet - Page 34

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1183_3
Product data sheet
12.2.3 Stall or Unstall Endpoint (40h to 4Fh/80h to 8Fh)
12.2.4 Validate Endpoint Buffer (61h to 6Fh)
Table 27.
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status register (see
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This flushes the buffer: if it is an OUT
buffer, it waits for a DATA0 PID; if it is an IN buffer, it writes a DATA0 PID.
Code: 40h to 4Fh — stall (control OUT, control IN, endpoints 1 to 14)
Code: 80h to 8Fh — unstall (control OUT, control IN, endpoints 1 to 14)
Transaction — none
Remark: When unstalling a stalled endpoint, issue the unstall command two times. The
first unstall command will update the Endpoint Status register in RAM. The second unstall
command will reset buffer pointers.
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the
buffer is valid and can be sent to the host, when the next IN token is received. For a
double-buffered endpoint, this command switches the current FIFO for CPU access.
Remark: For special aspects of the control IN endpoint, see
Bit
7
6
5
4
3
2
1
0
Symbol
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVERWRITE This bit is set by hardware. Logic 1 indicates that a new set-up packet has
SETUPT
CPUBUF
-
Endpoint Status register: bit description
Description
This bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not
stalled).
Set by a Stall Endpoint command. Cleared by an Unstall Endpoint
command. The endpoint is automatically unstalled on receiving a SETUP
token.
Logic 1 indicates that the secondary endpoint buffer is full.
Logic 1 indicates that the primary endpoint buffer is full.
This bit indicates the data PID of the next packet (0 = DATA0 PID, 1 =
DATA1 PID).
overwritten the previous set-up information, before it was acknowledged or
before the endpoint was stalled. This bit is cleared by reading, if writing the
set-up data has finished.
Firmware must check this bit before sending an Acknowledge Setup
command or stalling the endpoint. On reading logic 1, firmware must stop
ongoing set-up actions and wait for a new set-up packet.
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for CPU access (0 =
primary buffer, 1 = secondary buffer).
reserved
Rev. 03 — 20 January 2009
Low-power USB Peripheral Controller with DMA
Table
26).
Section
© ST-NXP Wireless 2009. All rights reserved.
9.5.
ISP1183
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