ISP1183BS STEricsson, ISP1183BS Datasheet - Page 33

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ISP1183BS

Manufacturer Part Number
ISP1183BS
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1183BS

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Table 26.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Endpoint Status register: bit allocation
12.2.2 Endpoint Status register (R: 50h to 5Fh)
EPSTAL
R
7
0
Table 24.
Table 25.
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer, or reading from an IN buffer. Any of these actions could
cause an incorrect operation. Data residing in an OUT buffer is meaningful only after a
successful transaction. Exception: during DMA access of a double-buffered endpoint, the
buffer pointer automatically points to the secondary buffer after reaching the end of the
primary buffer.
This command reads the status of an endpoint FIFO. The command accesses the
Endpoint Status register, the bit allocation of which is shown in
Endpoint Status register will clear the interrupt bit set for the corresponding endpoint in the
Interrupt register (see
All bits of the Endpoint Status register are read-only. Bit EPSTAL is controlled by the Stall
or Unstall commands and by the reception of a SETUP token (see
Code: 50h to 5Fh — read (control OUT, control IN, endpoints 1 to 14)
Transaction — read 1 byte
Byte # (8-bit bus)
0
1
2
3
:
(N + 1)
A0
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
:
EPFULL1
R
6
0
Phase
command
data
data
data
data
data
data
:
Endpoint FIFO organization
Example of endpoint FIFO access
EPFULL0
R
5
0
Rev. 03 — 20 January 2009
Table
Bus lines
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
:
46).
DATA_PID
R
4
0
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
:
data byte N
Low-power USB Peripheral Controller with DMA
Byte #
-
0
1
2
3
4
5
:
WRITE
OVER
R
3
0
Description
command code (00h to 1Fh)
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte 3
data byte 4
:
SETUPT
R
2
0
Table
CPUBUF
Section
© ST-NXP Wireless 2009. All rights reserved.
26. Reading the
R
1
0
ISP1183
12.2.3).
reserved
R
0
0
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