W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 66

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 3:
Bit 2:
Bit 1:
Bit 0:
6.3.4.3. Reg3 - Sets Select Register (SSR)
Reading this register returns E0
6.3.4.4. Reg4 - Advanced UART Control Register 2 (ADCR2)
Bit 7:
Bit 6:
default Value
Advanced
Reset Value
MODE
UART
REG.
SSR
DMATHL
DIS_BACK
0
1
ALOOP - All mode Loopback
Write to 1 enables loopback in all modes.
DMATHL - DMA Threshold Level
Sets DMA threshold level as shown in the table below.
DMA_F - DMA Fairness
ADV_SL - Advanced mode Select
Write to 1 selects advanced mode.
DIS_BACK - Disable Backward Operation
Write to 1, read or write BLL or BHL (Baud rate Divisor Latch Register, in Set1.Reg0~1),
will disable backward legacy UART mode. When using legacy SIR/ASK-IR mode, this bit
should be set to 1 to avoid backward operation.
Reserved, write 0.
SSR7
BIT 7
BIT 7
1
0
DMA_F
SSR6
BIT 6
BIT 6
0
1
1
0
-
16
. Write it to select other register Set.
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
16-Byte
SSR5
BIT 5
BIT 5
13
23
1
0
TX FIFO THRESHOLD
DMA request (DREQ) is forced inactive after 10.5us
SSR4
BIT 4
BIT 4
0
0
- 59 -
W83877ATF/W83877ATG
No effect on DMA request.
Function Description
SSR3
BIT 3
BIT 3
32-Byte
0
0
Publication Release Date:November 2006
13
7
SSR2
BIT 2
BIT 2
0
0
RX FIFO THRESHOLD
SRR1
BIT 1
BIT 1
(16/32-Byte)
0
0
10
4
Version 1.0
SRR0
BIT 0
BIT 0
0
0