W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 62

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Bit 2:
Bit 1, 0:
6.3.2.7. Set0.Reg6 - Handshake Status Register (HSR)
Legacy/Advanced UART Register: These registers are defined the same as in the previous
description.
6.3.2.8. Set0.Reg7 - User Defined Register (UDR/AUDR)
Legacy UART Register: These registers are defined the same as in the previous description.
Advanced UART Register:
Bit 7
Bit 6
Advanced
Advanced
Reset Value
Reset Value
Legacy
Legacy
MODE
MODE
UART
UART
UART
UART
MIR, FIR modes:
MIR, FIR modes:
MIR, FIR modes:
FLC_ACT UNDRN
CRC_ERR - CRC Error
Set to 1 when an attached CRC is error.
OER - Overrun Error, RDR - RBR Data Ready
Definitions are same as for legacy UART.
FLC_ACT - Flow Control Active
Set to 1 when flow control occurs. Clear to 0 when this register is read. Note that this will
be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR mode or
when MIR/FIR mode operated in DMA function switches to SIR mode.
UNDRN - Underrun
Set to 1 when transmitter is empty and not set S_FEND (in this register bit 3) operated in
PIO mode or not TC (Terminal Count) operated in DMA mode. Clear to 0 when write to 1.
BIT 7
DCD
DCD
Bit 7
B7
0
0
BIT 6
Bit 6
B6
RI
RI
0
0
RX_BSY/
RX_IP
BIT 5
DSR
DSR
Bit 5
B5
0
0
LST_FE/
RX_PD
BIT 4
CTS
CTS
Bit 4
B4
0
0
- 55 -
W83877ATF/W83877ATG
S_FEND
TDCD
TDCD
BIT 3
Bit 3
B3
0
0
Publication Release Date:November 2006
FERI
FERI
BIT 2
Bit 2
B2
0
0
0
LB_SF
TDSR
TDSR
BIT 1
Bit 1
B1
0
0
Version 1.0
RX_TO
TCTS
TCTS
BIT 0
Bit 0
B0
0
0