W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 112

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

11.2.3 Configuration Register 2 (CR2), default = 00H
When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed
through EFDR. This register is reserved.
11.2.4 Configuration Register 3 (CR3), default = 30H
When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed
through EFDR. The bit definitions are as follows:
Bit 7-bit 6: Reserved.
EPPVER (Bit 5):
This bit selects the EPP version of parallel port:
Bit 4: Reserved.
Bit 3-bit 2: Reserved.
SUAMIDI (Bit 1):
This bit selects the clock divide rate of UARTA.
SUBMIDI (Bit 0):
This bit selects the clock divide rate of UARTB.
0
1
0
1
0
1
Selects the EPP 1.9 version
Selects the EPP 1.7 version (default)
Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default)
Enables MIDI support, UARTA clock = 24 MHz divided by 12
Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default)
Dnables MIDI support, UARTB clock = 24 MHz divided by 12
7
6
5
4
3
- 105 -
2
W83877ATF/W83877ATG
1
0
Publication Release Date:November 2006
SUBMIDI
SUAMIDI
reserved
reserved
reserved
EPPVER
reserved
reserved
Version 1.0