W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 45

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.2
TABLE 3-1 UART Register Bit Map
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 mode.
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
BDLAB = 0
ADDRESS BASE
C
D
A
A
B
E
F
8
9
8
9
8
REGISTER
Register Address
Latch High
(Read Only)
(Read Only)
(Write Only)
UART FIFO
(Write Only)
Transmitter
Handshake
Handshake
Latch Low
Baudrate
Receiver
Register
Register
Interrupt
Register
Interrupt
Register
Register
Register
Register
Register
Register
Register
Baudrate
Defined
Control
Control
Control
Control
Divisor
Divisor
Status
Status
Status
Buffer
Buffer
UART
UART
User
RBR
UCR
HCR
USR
HSR
UDR
TBR
UFR
BHL
ICR
BLL
ISR
RX Data
RBR Data
RBR Data
TX Data
Terminal
Toggling
Interrupt
(ERDRI)
Interrupt
Pending
(TCTS)
(DLS0)
Enable
Enable
Length
Ready
Ready
Ready
Select
(RDR)
(DTR)
FIFO
"0" if
Data
Data
Bit 0
Bit 0
Bit 0
CTS
Bit 0
Bit 0
Bit 8
0
RX Data
(ETBREI)
Toggling
Interrupt
Interrupt
Request
TX Data
Overrun
(TDSR)
(DLS1)
Enable
Length
Empty
Status
RCVR
Select
(OER)
Bit (0)
Reset
(RTS)
FIFO
Send
Error
Data
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
1
BIT NUMBER
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
(EUSRI)
Interrupt
TX Data
Multiple
(MSBE)
(PBER)
Interrupt
Enable
Enable
(FERI)
Status
Bit (1)
Reset
Bit 10
XMIT
FIFO
Input
Edge
Error
Bit 2
Bit 2
Bit 2
Bit 2
- 38 -
USR
RI
2
W83877ATF/W83877ATG
RX Data
Toggling
TX Data
Interrupt
(EHSRI)
Interrupt
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
(PBE)
Parity
Bit 11
Mode
DMA
Error
DCD
Bit 3
Bit 3
HSR
Bit 3
Bit 3
IRQ
Bit
Bit
3
Loopback
Reserved Reversed
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(EPE)
(SBD)
Parity
(CTS)
Bit 12
Silent
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Bit 13
Parity
Bit 5
Bit 5
Bit 5
Bit 5
TBR
5
0
0
0
RX Data
Indicator
TX Data
Enabled
Interrupt
Silence
(TSRE)
Enable
FIFOs
Active
Empty
(SSE)
Bit 14
(LSB)
Level
Ring
Bit 6
Bit 6
TSR
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Access Bit
RX Data
Baud rate
Indication
(RFEI) **
(BDLAB)
RX FIFO
Interrupt
TX Data
Enabled
Divisor
Carrier
Detect
FIFOs
Active
(MSB)
(DCD)
Bit 15
Level
Latch
Error
Data
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0