W83877ATG Nuvoton Technology Corporation of America, W83877ATG Datasheet - Page 46

• Manufacturer Part Number: W83877ATG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83877ATG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.2.1
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only SOUT is
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or
Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in
format) from the divisor latches of the baud rate generator during a read or write operation.
When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the
Interrupt Control Register can be accessed.
affected by this bit; the transmitter is not affected.
(1) if EPE is a logical 1, the parity bit is fixed as a logical 0 to transmit and check.
(2) if EPE is a logical 0, the parity bit is fixed as a logical 1 to transmit and check.
3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When
the bit is reset, an odd number of logic 1's are sent or checked.
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same
position as the transmitter will be detected.
received.
(1) If MSBE is set to a logical 0, one stop bit is sent and checked.
(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent and
(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and
each serial character.
UART Control Register (UCR) (Read/Write)
checked.
checked.
7
6
5
4
3
2
1
0
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Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
W83877ATF/W83877ATG
Publication Release Date:November 2006
Version 1.0