MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 12

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications – I
Table 3:
PDF: 09005aef80a41b59/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN
Description
Standby current
Active standby
current
Operational
current
Operational
current
Operational
current
Burst refresh
current
Distributed
refresh current
Operating burst
write current
example
Operating burst
write current
example
Operating burst
write current
example
Operating burst
read current
example
Operating burst
read current
example
Operating burst
read current
example
I
Notes are on page 13
DD
Operating Conditions and Maximum Limits—Rev. A
Conditions
t
toggling
t
address incremented and half address/
data change once every 4 clock cycles
BL = 2;
active; Half address changes once per
t
BL = 4;
active; Half address changes once per
t
BL = 8;
active; Half address changes once per
t
t
refresh; Data inputs are switching
t
refresh; Half address/data toggle
BL = 2;
bank access; Half of address bits change
every clock cycle; Continuous data
BL = 4;
bank access; Half of address bits change
every 2 clock cycles; Continuous data
BL = 8;
bank access; Half of address bits change
every 4 clock cycles; Continuous data
BL = 2; Cyclic bank access; Half of
address bits change every clock cycle;
Measurement is taken during
continuous READ
BL = 4; Cyclic bank access; Half of
address bits change every 2 clocks;
Measurement is taken during
continuous READ
BL = 8; Cyclic bank access; Half of
address bits change every 4 clock cycles;
Measurement is taken during
continuous READ
CK = Idle; All banks idle; No inputs
CK = MIN, CS# = 1; No commands; Bank
RC; Read followed by write sequence
RC; Read followed by write sequence
RC; Read followed by write sequence
CK = MIN;
CK = MIN;
t
t
t
t
t
t
CK = MIN;
CK = MIN;
CK = MIN;
CK = MIN;
CK = MIN;
CK = MIN;
t
t
RC = MIN; Cyclic bank
RC = MIN; Single bank
t
t
t
t
t
t
RC = MIN; 1 bank
RC = MIN; 1 bank
RC = MIN; 1 bank
RC = MIN; Cyclic
RC = MIN; Cyclic
RC = MIN; Cyclic
DD
288Mb: x18 2.5V V
12
I
I
I
DD2R
DD4R
DD8R
I
I
I
I
I
I
I
I
I
DD2W
DD4W
DD8W
I
I
I
I
I
I
I
DD2W
DD4W
DD8W
DD2R
DD4R
DD8R
I
I
I
I
I
REF1
REF2
I
I
DD1
DD2
DD3
REF1
REF2
SB1
SB2
DD1
DD2
DD3
Symbol
SB1
SB2
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
(V
DD
DD
DD
(V
(V
(V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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EXT
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DD
EXT
EXT
EXT
EXT
EXT
DD
DD
DD
DD
DD
EXT
EXT
EXT
EXT
EXT
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DD
DD
) x18
) x18
) x18
)
)
)
)
)
)
)
)
)
EXT
)
)
)
)
)
)
)
)
)
)
)
)
)
)
, 1.8V V
288
348
362
408
785
133
325
970
100
779
668
860
100
680
570
-25
Electrical Specifications – I
48
26
26
41
48
55
48
88
60
88
60
DD
, HSTL, SIO, RLDRAM II
233
305
319
368
615
111
267
819
609
525
735
525
450
-33
48
26
26
36
42
48
42
90
77
51
90
77
51
©2003Micron Technology, Inc. All rights reserved.
189
255
269
286
430
105
221
597
439
364
525
380
310
48
26
26
36
42
48
42
69
63
40
69
63
40
-5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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