XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 372

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Advanced SelectIO Logic Resources
Table 8-6: OSERDES Port List and Definitions
372
OQ
SHIFTOUT1
SHIFTOUT2
TQ
CLK
CLKDIV
D1 – D6
OCE
REV
SHIFTIN1
SHIFTIN2
SR
T1 to T4
TCE
Port Name
OSERDES Ports
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Data Path Output - OQ
3-state Control Output - TQ
High-Speed Clock Input - CLK
Divided Clock Input - CLKDIV
Table 8-6
The OQ port is the data output port of the OSERDES module. Data at the input port D1 will
appear first at OQ. This port connects the output of the data parallel-to-serial converter to
the data input of the IOB.
This port is the 3-state control output of the OSERDES module. When used, this port
connects the output of the 3-state parallel-to-serial converter to the control/3-state input of
the IOB.
This high-speed clock input drives the serial side of the parallel-to-serial converters.
This divided high-speed clock input drives the parallel side of the parallel-to-serial
converters. This clock is the divided version of the clock connected to the CLK port.
1 (each)
1 (each)
Width
1
1
1
1
1
1
1
1
1
1
1
1
lists the available ports in the OSERDES primitive.
Data path output. See
Carry out for data width expansion. Connect to SHIFTIN1 of master OSERDES.
See
Carry out for data width expansion. Connect to SHIFTIN2 of master OSERDES.
See
3-state control output. See
High-speed clock input. See
Divided clock input. Clocks delay element, deserialized data, Bitslip submodule,
and CE unit. See
Parallel data inputs. See
Output data clock enable. See
Reverse SR pin. Not available in the OSERDES block.
Carry input for data width expansion. Connect to SHIFTOUT1 of slave OSERDES.
See
Carry input for data width expansion. Connect to SHIFTOUT2 of slave OSERDES.
See
Active High reset.
Parallel 3-state inputs. See
3-state clock enable. See
OSERDES Width
OSERDES Width
OSERDES Width
OSERDES Width
www.xilinx.com
Divided Clock Input -
Expansion.
Expansion.
Expansion.
Expansion.
Data Path Output -
3-state Signal Clock Enable -
Parallel Data Inputs - D1 to
3-state Control Output -
Parallel 3-state Inputs - T1 to
High-Speed Clock Input -
Output Data Clock Enable -
Description
CLKDIV.
OQ.
TQ.
D6.
TCE.
CLK.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T4.
OCE.