XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 127

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Cascade In - CASCADEINLAT[A|B] and CASCADEINREG[A|B]
Cascade Out - CASCADEOUTLAT[A|B] and CASCADEOUTREG[A|B]
Inverting Control Pins
GSR
Unused Inputs
The CASCADEIN pins are used to connect two block RAMs to form the 64K x 1 mode
(Figure
connected to the CASCADEOUT pins of the LOWER block RAM of the same port. When
cascade mode is not used, this pin does not need to be connected. Refer to the
Block RAM
X-Ref Target - Figure 4-10
The CASCADEOUT pins are used to connect two block RAMs to form the 64K x 1 mode.
This pin is used when the block RAM is the LOWER block RAM, and is connected to the
CASCADEIN pins of the UPPER block RAM of the same port. When cascade mode is not
used, this pin does not need to be connected. Refer to the
further information.
For each port, the six control pins (CLK, EN, and SSR) each have an individual inversion
option. EN and SSR control signals can be configured as active High or Low, and the clock
can be active on a rising or falling edge (active High on rising edge by default), without
requiring other logic resources.
The global set/reset (GSR) signal of a Virtex-5 device is an asynchronous global signal that
is active at the end of device configuration. The GSR can also restore the initial Virtex-5
device state at any time. The GSR signal initializes the output latches to the INIT (simple
dual port), or to the INIT_A and INIT_B value (true dual port.) See
A GSR signal has no impact on internal memory contents. Because it is a global signal, the
GSR has no input pin at the functional level (block RAM primitive).
Unused data and/or address inputs should be connected High.
4-10.) This pin is used when the block RAM is the UPPER block RAM, and is
for further information.
CASCADEOUTLATA/B
CASCADEINLATA/B
Figure 4-10: Two RAMB36s Cascaded
www.xilinx.com
2
RAMB36
RAMB36
Upper
Lower
CASCADEINREGA/B
CASCADEOUTREGA/B
2
Cascadable Block RAM
ug190_4_12_040606
Block RAM Port Signals
Block RAM
Cascadable
Attributes.
for
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